RU2688236C1 - Device for counting minimum intensity of placement in multiprocessor cubic cyclic systems in unidirectional transmission of information - Google Patents

Abstract

FIELD: physics.

SUBSTANCE: invention relates to digital computer engineering and is intended for simulating combinatorial tasks when designing computer systems. Device comprising a first and a second shift register, a permutation generating unit, a persistent memory unit, a best version storage unit, a switch, an ALU, an arc selection decoder, a reversible cell counter, a random-access memory unit, a topology counter, first and second distance meters, a multiplier, an adder, minimum link length register, a first comparison element, a subtractor, triggers for counting start, a topology setting mode and a link length register, a second comparison element, an arcs counter, arc lock decoder, arc number register, minimum weight register, graph electronic model, group of 1..n OR elements, group 1..m of AND elements, a minimum value unit containing the first RAM of circular cyclic system, RAM of cyclic fragment, SR mode trigger, multiplier, distance counter, subtracting counter.

EFFECT: wider range of technical means.

1 cl, 10 dwg

Description

The invention relates to the field of digital computing and is intended for modeling combinatorial problems in the design of computing systems (VS).

A homogeneous environment element is known, which includes an input signal processing unit, an end point feature memorization unit, an output logic block, a trace recording trigger, a current allocation estimation unit, an information transfer unit, inputs, outputs, a control input, information inputs, information outputs, an indicator output ( AS 1291957 USSR CL G 06 F 7/00, published 23.02.87, BI No. 7).

The disadvantage of this element is the narrow scope, due to the limited number of criteria for assessing the degree of optimality of placement.

Closest to the proposed device to the technical essence is a device for the formation of suboptimal placement and its evaluation, which contains the permutation formation unit, the permanent memory block, the switch, the arithmetic logic unit (ALU), the best memory block, the arc selector decoder, the reversible cell counter are entered , memory block, topology counter, first and second distance counters, multiplier, adder, register of the minimum length of links, first comparison element, subtractor, trigger ep account start, mode trigger, topology set trigger, link length register, second comparison element, arc counter, arc lock decoder, arc number register, minimum weight register, AND group, first and second AND elements, second block of OR elements, third AND element, first and second one-shot, first, second and third delay elements, two shift registers, OR element and group of OR elements, electronic graph model (EMG) containing m electronic arc models, with l-th electronic arc model (l = 1 , 2, ..., m) contains trig ep arc lock register arc weights arc lock register, a first AND gate, a second AND gate, an OR gate (RF Patent №2193796, Cl. G 06 F 17/10, 7/38, publ. November 27, 2002, BI No. 33).

The disadvantage of this device is the narrow scope, due to the lack of funds for calculating the minimum value of the intensity of accommodation in multiprocessor cubic cyclic systems (MCC) with the unidirectional transmission of information.

An object of the invention is to expand the scope of the device by introducing funds to calculate the minimum value of the intensity of accommodation in multiprocessor cubic cyclic systems with unidirectional transmission of information according to the criterion of minimizing the intensity of interaction between processes and data.

The technical problem is solved by the fact that in a device for calculating the minimum value of the intensity of placement in multiprocessor cubic cyclic systems with unidirectional information transfer, containing a matrix of m rows and n columns of elements of a homogeneous medium, n units of counting units, the unit finding the maximum, adder, memory block, wherein the permutation control inputs of the columns of the matrix of elements of a homogeneous medium are connected to the permutation control input of the device columns, the row permutation control inputs are ma the trinkets of the homogeneous environment elements are connected to the control input of the permutation of the device rows, the installation inputs of the matrix of the homogeneous environment elements are connected to the installation input of the device, the information inputs of the matrix of the homogeneous environment elements are connected to the device recording input, the indicator outputs of the j-th column (j = 1,2, ..., n) matrices of elements of a homogeneous medium are connected to the input of the jth unit counting unit, the output of which is connected to the jth input of the maximum finding block and the jth input of the adder, the outputs of which are connected to the output of ma xmaximal length of the device edge and the output of the total length of the device edges, respectively, the control input of the memory block is connected to the control input of the device, the information outputs of the i-th row elements (i = 1,2, ..., m) of the matrix of homogeneous environment elements are connected to i- The information input of the memory block, the output of which is connected to the information output of the device, is additionally introduced a minimum value block containing the first RAM of the ring cyclic system, the RAM of the cyclic fragment, the first column counter, second swarm column counter, first row counter, second column counter, minimum value adder, first AND element, second ring cyclic system RAM, third column of adjacency matrix columns, second row counter, first and second row number counter, count of cyclic sections, SR- trigger mode, the second element And, the multiplier, the distance counter, subtractive counter, and the output of the RAM block is connected to the first input of the second element And the second input of which is connected to the overflow output of the first the count of the number of rows, the second input of the first 66 element I and to the e-input of the counter of the number of cyclic sections, the counting input of which is connected to the overflow output of the second column counter, the e-input of which is connected to the output of the first And element and to the e-input of the second column counter, the overflow output of which is connected to the counting input of the second column counter, the output of which is connected to the a1 input of a cyclic fragment RAM, a2-input of which is connected to the output of the second column counter whose counting input is connected to cycles At the device input, the counting input of the distance counter is connected to the clock input of the device, the output of the distance counter is connected to the first input of the multiplier and the counting input of the subtracting counter, the overflow output of which is connected to the s-input of the distance counter, the second input of the multiplier is connected to the output of the operating memory, the output of the second element And is connected to the S-input of the SR-mode trigger, the R-input of which is connected to the overflow output of the second counter of the number of rows, the counting input of which is connected to the overflow output of the first column counter, the e-input of which is connected to the direct output SR-mode trigger, the reverse output of which is connected to the e-input of the third column counter, the counting input of which is connected to the device’s clock input, the network input of the first column counter and the s-inputs of the first column counter The RAM of the ring cyclic system and the second RAM of the ring cyclic system, the D input of which is connected to the output of the multiplier and the D input of the first RAM of the ring cyclic system, a1 input of which is connected to the output of the first row counter, a2 input of the first RAM ring cyclic system is connected to the output of the first column counter, a1 input of the second RAM of the ring cyclic system is connected to the output of the second row counter, the counting input of which is connected to the output of the first row number counter, D-input of the cyclic fragment RAM, connected to the output of the memory block, output The RAM of the fragment is connected to the first input of the adder, the second and third inputs of the adder are connected to the outputs of the first RAM of the ring cyclic system and the second RAM of the ring cyclic system, output The adder is connected to the output of the VUU, where a decision is made on further actions of the multiprocessor cubic cyclic system, the output of the overflow of the counter of the number of cyclic sections is connected to the output of the overflow of the device.

The device according to claim 1, characterized in that the electronic model of the graph contains m electronic models of the arc, and the lth electronic model of the arc (l = 1, 2, ..., m) contains the arc lock trigger, the arc weight register, the arc lock register, the first element is AND, the second element is AND, the element is OR, and the inputs of the first element are AND are connected to the corresponding inputs of the device graph, the output of the first element is AND is connected to the synchronous input of the arc weight register and to the installation input of the arc lock trigger, the reset input of which is connected to the lth arc lock input the electronic model of the graph, the data input of the arc weight register is connected to the lth input of the arc weight of the device, the first input of the OR element is connected to the lth control input of the electronic graph model, and the second input of the OR element is connected to the output of the second AND element, the first input of which is connected with the direct output of the arc lock trigger and with the enable input of the arc lock register, the second input of the second element I is connected to the lth arc selection input of the electronic model of the graph, the reset input of the arc lock register is connected to the lth device reset input, output the arc lock register is connected to the lth arc weight output of the electronic model of the graph, which is also connected to the arc weight register output; the OR element output is connected to the enable input of the arc weight register.

The invention is illustrated by drawings, where in FIG. 1 shows an example of the original task graph; FIG. 2 shows an example of the description of the adjacency matrix of the graph shown in FIG. 1; in fig. 2 shows the adjacency matrix W of a ring cubic system, corresponding to the graph shown in FIG. in fig. 3 shows the distance matrix for a ring cubic system consisting of six processors; Fig 4 shows an example of a multiprocessor cubic cyclic system; FIG. 5 represents a cyclic representation of a cubic cyclic multiprocessor system; FIG. 6 describes the adjacency matrix for the cyclic fragment shown in FIG. five; FIG. 7. Shows the distance matrix for the cyclic fragment shown in FIG. five; in fig. 8, fig. 9 and FIG. 10 represents a device for calculating the minimum value of the intensity of placement in multiprocessor cubic cyclic systems.

General features of the invention are as follows.

The proposed device can be used in the field of VC design, for example, when placing processes (algorithms, tasks, data, files, etc.). The device additionally allows you to perform the calculation of the minimum value of the intensity of placement in multiprocessor cubic cyclic systems.

которого соответствуют подзадачам (подалгоритмам, подпрограммам и т.п.), а дуги

задают управляющие и/или информационные связи между подзадачами и фактически являются каналами передачи данных. Граф G может быть описан матрицей смежности

, где

;

– объем передаваемых данных между i-м и j-м процессорным модулем (фиг. 2).The initial task (process, algorithm, program) is represented as a directional weighted graph G = <X, E> (Fig. 1), the vertices

which correspond to subtasks (subalgorithms, subroutines, etc.), and arcs

specify control and / or informational connections between subtasks and actually are data transfer channels. The graph G can be described by the adjacency matrix.

where

;

- the amount of data transferred between the i-th and j-th processor module (Fig. 2).

(фиг. 3)The topological model of MCC (location) is defined by the distance matrix D1. The elements of the distance matrix D1 = || d1 _{i, j} || _{n × n} for a cubic system are formed by the formula

(Fig. 3)

вершин которого вместо одного элемента, что характерно для полного гиперкуба, представляется циклом из d связанных вершин. Каждый из элементов в таком цикле имеет по три двунаправленных канала связи, два из которых подключено к соседним элементам, принадлежащим общему с данным элементом циклу, а третий канал пересекает гиперкуб в одном из d измерений и соединяет рассматриваемый элемент с соответствующим элементом другого цикла.The cubic cyclic system (FIG. 4) is a Boolean cube (q = 2) of dimension d, each of

whose vertices instead of one element, which is typical for a full hypercube, is represented by a cycle of d connected vertices. Each of the elements in such a cycle has three bidirectional communication channels, two of which are connected to neighboring elements belonging to the common cycle with this element, and the third channel crosses the hypercube in one of the d dimensions and connects the element in question with the corresponding element of the other cycle.

, где

;

– объем передаваемых данных между i-м и j-м процессорным модулем (фиг. 6). Топологическая модель цикла описывается матрицей расстояний

для кубической системы образуются по формуле

(фиг. 7). На фиг. 5, 6 и 7 представлена матрица смежности и матрица расстояний, не соответствующая графу, изображенному на фигурах 1-3. Это сделано для общего понимания сути циклического фрагмента КЦС.For the mathematical description of the cyclic fragment of the cubic system (Fig. 5), we introduce the adjacency matrix

where

;

- the amount of data transferred between the i-th and j-th processor module (Fig. 6). The topological model of a cycle is described by a distance matrix.

for a cubic system are formed by the formula

(Fig. 7). FIG. Figures 5, 6 and 7 show the adjacency matrix and the distance matrix not corresponding to the graph shown in Figures 1-3. This is done for a general understanding of the essence of the cyclic fragment of MCC.

, где множество вершин

соответствует процессорным модулям, а множество дуг V – межмодульным связям,

Множество

разбивается на два непересекающихся подмножества

, где

– множество основных процессоров,

– множество циклических фрагментов кубической системы, причем фиксируется

Упорядочим множества процессоров P и L в виде матриц

и

соответственно. Множество

представим объединением указанных матриц следующим образом:The MCC topology is given by the graph

where many vertices

corresponds to the processor modules, and the set of arcs V - intermodular connections,

Lots of

broken into two disjoint subsets

where

- many main processors,

- the set of cyclic fragments of the cubic system, and fixed

Order the sets of processors P and L in the form of matrices

and

respectively. Lots of

Let us represent the union of these matrices as follows:

(1)

(one)

соответствует одна из циклических вершин КЦС.Thus, from (1) it follows that any vertex

corresponds to one of the cyclic vertices of the MCC.

Thus, according to (1), the placement of the set of interrelated subroutines described by the graph X in multiprocessor cubic cyclic systems is given by the mapping:

, (2)

, (2)

which assigns to each subprogram one of the processors (the main processor or the cyclic fragment processor MCC).

The minimum value of the intensity of accommodation L ^* regardless of the topological model is determined by the formula:

,

, (3)

,

– векторы, первый из которых содержит ненулевые элементы матрицы смежности W1, расположенные по убыванию, а второй – ненулевые элементы матрицы расстояний D1, расположенные по возрастанию; k – порядковый номер элемента; t=

- мощность множества дуг E (количество дуг). При этом фактическое значение интенсивности размещения всегда либо больше, либо равно L^*.где максимум в фигурных скобках представляет собой наибольшую частную коммуникационную задержку для заданного отображения β.Where

,

- vectors, the first of which contains non-zero elements of the adjacency matrix W1, arranged in descending order, and the second - non-zero elements of the distance matrix D1, arranged in increasing order; k is the ordinal number of the element; t =

- the power of the set of arcs E (the number of arcs). At the same time, the actual value of the placement rate is always either greater than or equal to L ^*. Where the maximum in curly brackets represents the largest private communication delay for a given mapping β.

Таким образом предложенный подход является удобным механизмом отслеживания качества получаемых вариантов размещений с последующей их оценкой на ВУУ и принятия решений о дальнейших действиях мультипроцессорной системы.The intensity of the real placement option will always be either more or less than the minimum value of the placement

Thus, the proposed approach is a convenient mechanism for tracking the quality of the received placement options with their subsequent evaluation at the VUU and making decisions about further actions of the multiprocessor system.

A device for calculating the minimum value of the intensity of placement in multiprocessor cubic cyclic systems with unidirectional information transfer contains the first shift register 1, the second shift register 2, the permutation generation unit (BFP), the permanent memory unit 4, the best option storage unit 5 (BLU), the switch 6, ALU 7, decoder 8 arc selection, reversible counter 9 cells, unit 10 RAM, counter 11 topology, first 12 and second 13 distance counters, multiplier 14, adder 15, register 16 minimum length Links, first comparison element 17, subtractor 18, counting trigger 19, mode trigger 23, topology setting trigger 24, link length register 25, second comparison element 26, arc counter 27, arc lock decoder 28, arc number register 29, register 30 minimum weights, electronic model 31 graph, group of elements OR 32.1 - 32.n, group of elements AND 33.1 - 33.m, first 34 and second 35 elements AND, second block of elements OR 36, third element And 37, first 41 and second 42 one-shot, the first 43, the second 44 and the third 45 delay elements, the first block of elements OR 46, and m outputs BFP 3 connected to the corresponding inputs of the block 4 permanent memory and the corresponding inputs BZLV 5, signaling output BFP 3 connected to the installation input of the trigger 19 start counting, the outputs of block 4 permanent memory connected to the corresponding inputs of the switch 6, the output of which is connected to the input of the ALU 7 whose output is connected to the information input of BZLV 5, and the output of BZLV 5 is connected to the first information input of ALU 7, the output of the shift register 1 is connected to the input of the shift register 2, the outputs of registers 1 and 2 from the first to the n-th connected to the first and second inputs of the elements OR 32.1 - 32.n respectively, the output of the overflow register 2 shift is connected to the control input of the ALU 7 and the control input of the BFP 3, the clock input 57 of the device is connected to the input of the register 1 shift, with the clock input of the BFP 3 and with the first inputs of the elements 34 and 35, the output of the counter 27 arcs connected to the input of the decoder 8 arc selection and the data input of the register 29 of the arc number, the output of the block of elements OR 36 is connected to the first input of the comparison element 17 and to the data input of the minimum weight register 30, output register 30 min The weighing weight is connected to the second input of the comparison element 17 and to the data input of the RAM block 10, the output of the delay element 43 is connected to the input of the minimum weight register 30 and to the input of the arc number register 29, the output of the third element 37 is connected to the minimum 30 weight and synchronous input of the register 29 of the arc number, the output of the arc number register 29 is connected to the information input of the arc lock decoder 28, the overflow output of the arc counter 27 is connected to the enable input of the arc lock decoder 28 and also with the input of the delay element 43, the first counting input of the reversible counter 9 cells and the recording input of the RAM block 10, the output of the AND element 34 is connected to the counting input of the counter 27 arcs and with the input of the delay element 44 whose output is connected to the second input of the And element 37, the first input of which is connected to the output of the comparison element 17, the second input of the AND element 34 is connected to the direct output of the trigger trigger 19, which is also connected to the second input of the AND element 35, the third input of the And element 34 is connected to the inverse output of the mode trigger 23, the direct output of which is connected to the third input of the element 35, the output of the element 35 is connected to the second counting input of the reversing counter of 9 cells, the output of which is connected to the address input of the main memory unit 10, the output of which is connected to the first input of the multiplier 14, the output of the distance counter 13 is connected to the second input of the multiplier 14, the output of which is connected to the first input of the adder 15, the second input of which is connected to the output of the register 16 of the minimum connection length and to the second input of the subtractor 18, the output of the adder 15 is connected to the data input The register 16 is the minimum length of the links, the output of the delay element 45 is connected to the synchronous input of the register 16 of the minimum length of the connections, the output of the AND element 35 and the counting input of the distance counter 12 is connected to the input of the delay element 45, the output of the one-vibrator 42 is connected to the synchronous input of the distance counter 12, the overflow output of which is connected to the counting inputs of the counter 11 topology, the counter 13 distances and to the input of the one-shot 42, the output of the counter 11 topology is connected to the input of the counter 12 distances, the input 51 of the device data is connected to the data input of the counter 1 1 topology, synchronization input of the counter 11 topology is connected to input 52 of the device installation, direct output of the topology trigger 24 is connected to the enable input of the counter 11 topology, the installation input of the topology trigger 24 is connected to the device installation input 49, reset input of the topology trigger 24 is connected to the input 50 of the device installation, the overflow output of the reversing counter of 9 cells is connected to the setup input of the mode trigger 23, the reset input of which is connected to the input 48 of the device installation, the output of the register 25 is the length of The lane is connected to the second input of the comparison element 26 and to the first input of the subtractor 18, the first input of the comparison element 26 is connected to the output of ALU 7 and the data input of the link length register 25, the output of the one-vibrator 41 is connected to the link length register 25, the reset start trigger input 19 connected to input 47 of the device installation, the lth output of the decoder 8 arc selection (l = 1, 2, ..., m) is connected to the lth input of the arc selection of the electronic model 31 of the graph, the lth output of the decoder 28 of the arc lock is connected to l th input blocking the arc of the electronic model of the 31 graph, the lth you The weight of the arc of the electronic model 31 of the graph is connected to the lth input of the block of elements OR 36 and the lth input of the block of elements OR 46, the output of the AND 33.l element is connected to the lth control input of the electronic model 31 of the graph, the output of the block of elements OR 46 connected to the second information input of the ALU 7, the output of the comparison element 26 is connected to the input of the one-vibrator 41, the outputs of the elements OR 32.1 - 32.n are connected to the corresponding inputs of the elements And 33.1 - 33.m, the output of the subtractor 18 is connected to the output 53 of the device link length, and also the additionally entered minimum block 58 It contains the first 59 RAM of the ring cyclic system, the cyclic fragment RAM 60, the first 61 column counter, the second 62 column counter, the first 63 row counter, the second 64 column counter, the adder 65 minimum value, the first 66 element And, the second 67 RAM circular cyclic systems, the third 68 column counter of the adjacency matrix, the second 69 row counter, the first 70 and second 71 row rows counter, the count of 72 number of cyclic plots, SR mode trigger 74, the second And 76 element, multiplier 77, distance counter 78, subtracting 79 counter , etc What is the output of the RAM block 10 connected to the first input of the second 76 element I, the second input of which is connected to the overflow output of the first 70 line count, the second input of the first 66 element I, and to the e-input of the counter 72 of the number of cyclic sections, the counting input of which is connected to the output of the overflow of the second 64 column counter, the e-input of which is connected to the output of the first 66 I element and to the e-input of the second 62 column counter, the output of the overflow of which is connected to the counting input of the second 64 column counter, the output of which It is connected to the a1 input of a cyclic fragment RAM 60, the a2 input of which is connected to the output of the second 62 column counter, the counting input of which is connected to the clock input 57 of the device, the counting input of the distance counter 78 connected to the clock 57 input of the device, the output of the distance counter 78 connected to the first input of the multiplier 77 and with the counting input of the subtracting 79 counter, the overflow output of which is connected to the s-input of the distance counter 78, the second input of the multiplier 77 is connected to the output of the main memory unit 10, the output of the second 76 element And soi inn with S-input SR-flip-flop 74 of the mode, the R-input of which is connected to the overflow output of the second 71 row count counter, the counting input of which is connected to the overflow output of the first 61 column counter, e-input of which is connected to the direct output SR-flip-flop 74 of the mode The reverse output of which is connected to the e-input of the third 68 column counter, the counting input of which is connected to the clock input 57 of the device, the network input of the counter of the first 61 column counter and to the s-inputs of the first 59 RAM of the ring cyclic system and the second 67 of RAM of the ring cycle system, the D-input of which is connected to the output of the multiplier 77 and the D-input of the first 59 RAM of the ring cyclic system, the a1-input of which is connected to the output of the first 63 row counter, a2-input of the first 59 of the RAM of the ring cyclic system is connected to the output of the first 61 column counter, a1 input of the second 67 RAM of a ring cyclic system is connected to the output of the second 69 row counter, the counting input of which is connected to the output of the first 70 counters of the number of rows, D-input of the RAM 60 of the cyclic fragment is connected to the output of the RAM 10 block, output O The loop memory 60 is connected to the first input of the adder 65, the second and third inputs of the adder 65 are connected to the outputs of the first 59 RAM of the ring cyclic system and the second 67 of the RAM of the ring cyclic system, the output of the adder 65 is connected to the output of the VUU, where the decision on further multiprocessor actions is made cubic cyclic system, the output of the overflow of the counter 72 of the number of cyclic sections connected to the output 73 of the overflow device.

The device according to claim 1, characterized in that the electronic model 31 of the graph (FIG. 9) contains m electronic models of the arc, and the electronic model 31.l of the arc (l = 1, 2, ..., m) contains the arc interlocking trigger 20.l , the arc weight register 21.l, the arc lock register 22.l, the first element AND 38.l, the second element AND 39.l, the element OR 40.l, and the inputs of the AND 38.l element are connected to the corresponding inputs 56.y and 56.z set the device graph (where y and z are the numbers of the starting and ending vertices of the l-th arc of the graph, respectively), the output of the And 38.l element is connected to the synchronous input of the arc weight register 21.l and from the mouth The main input of the arc lock trigger 20.l, the reset input of which is connected to the lth block input arc of the model 31, the data register 21.l of the arc weight is connected to the input 54.l of the arc weight of the device, the first input of the OR 40.l element is connected to The lth control input of the model is 31, and the second input of the OR 40.l element is connected to the output of the AND 39.l element, the first input of which is connected to the direct output of the trigger 20. l arc lock and to the enable input of the arc lock register 22.l, the second the input element And 39.l is connected to the lth input of the arc selection model 31, the reset input of the register 22.l block The arc is connected to the device reset input 55.l, the arc lock register 22.l output is connected to the model 31 weight arc output, which is also connected to the output of the arc weight register 21.l, the output element OR 40.l is connected to the resolving register entry 21.l arc weight.

The purpose of the elements and units of the device (figure 1) is as follows.

The first and second registers 1 and 2 of the shift are necessary for the implementation of the sequential search for pairs of vertices of the digraph G.

Block 3 of the formation of permutations iterates through all possible locations of the vertices of the graph G according to the positions of a given topological model.

Block 4 permanent memory stores the binary codes of position numbers.

Block 5 memorization of the best option is used to memorize the best at the moment option placement.

Switch 6 provides sequential cheating from the block of 4 codes of numbers of selectable positions for transfer to ALU 7.

The arithmetic logic unit 7 is necessary to determine the distance between the positions in which the selected vertices of the graph are placed, and to calculate the length of the connections L for the formed placement variant. This device is able to determine distances between positions for both weighted and unweighted graphs.

The decoder 8 select the arc together with the counter 27 arcs are designed to select from the EMG 31 arc with the number recorded in the counter 27.

A reversible counter of 9 cells serves to organize the sequential search of the addresses of the RAM block 10 in the forward and reverse order, respectively, when writing information and reading it.

Block 10 RAM is used to store the weights w _{i, j of} arcs of the digraph G in ascending order of their values.

с заданным значением (для кольцевой топологической модели общее число таких элементов постоянно и составляет n, для линейной это число уменьшается от n-1 для

=1 до 1 для

=n-1). The counter 11 of the topology is necessary for counting and transmitting to the counter 12 the number of processed vector elements.

with a given value (for a ring topological model, the total number of such elements is constant and is n, for a linear one, this number decreases from n-1 for

= 1 to 1 for

= n-1).

).The first distance counter 12 and the second distance counter 13 are designed to organize the search in an increasing order of nonzero elements of the distance matrix D (thus, a vector is formed at the output of the counter 13

).

) из счетчика 13 расстояний.The multiplier 14 is required to multiply the weight of the arc from the RAM block 10 by the distance between the positions of the topological model (the vector element

) from the counter 13 distances.

The adder 15 is designed to sum the values from the multiplier 14 and register 16.

Register 16 of the minimum length of links stores the value of the minimum possible length of links L ^* for a given graph.

The first comparison element 17 serves to compare the weight of the current arc with the lowest weight currently recorded in register 30.

Subtractor 18 is used to find the degree of optimality of placement ξ by the formula (2). The value of L ^* comes from the output of the register 16 of the minimum length of links, L comes from the output of the register 25 of the length of links.

The trigger 19 of the beginning of the account is used to indicate the transition from the mode of formation of accommodation in the mode of its evaluation.

The trigger 23 mode is used to store the sign of the current operation. If the trigger 23 is set to zero, this means writing the weights of the arcs in ascending order to the RAM block 10, and to the unit - finding the minimum possible length L ^* by the formula (1).

A trigger 24 for specifying a topology is intended to specify the type of topological model: if trigger 24 is set to one, this means the choice of a linear model, to zero, a ring model.

The arc lock decoder 28 is designed to select the arc to be blocked in the current cycle of the device operation.

Register 29 of the arc number is used to store the arc number with the minimum weight selected in the current cycle of the device.

A minimum weight register 30 is required to store the minimum current weight of the arc.

The group of elements OR 32.1 - 32.n is necessary for combining the corresponding signals from registers 1 and 2.

The group of elements AND 33.1 - 33.m is used to select the corresponding arcs of the graph G from the signals from the elements OR 32.1 - 32.n.

The first and second elements And 34 and 35 are needed to block the transmission of pulses from the clock input 57 of the device to the elements and blocks, ensuring the ordering of the weights of the arcs of the graph in block 10.

The second block of elements OR 36 is necessary to connect the weight of the current arc to the element 17 of the comparison and the register 30.

The third element And 37 is designed to block the passage of pulses to the synchronization inputs of registers 29 and 30.

The electronic model 31 of the graph serves to model the topology of the graph G representing the object to be placed (Fig. 2).

The first and second one-shot 41 and 42 are necessary for the formation of pulses that control the recording of information in the register 25 and the counter 12, respectively.

The first delay element 43 serves to delay the overflow pulse from the counter of 27 arcs for a time sufficient to ensure that the arc is blocked by the decoder 28 and the minimum weight is written from the register 30 to the RAM block 10.

The second delay element 44 is needed to delay the clock pulse for a time sufficient to ensure the selection of the next arc and compare its weight with the minimum weight recorded in register 30.

The third delay element 45 provides a delay of the pulse arriving at the register 16 of the minimum length of the connections for a time sufficient for counting and adding the next term of formula (1) with the multiplier 14 and the adder 15.

The first block of elements OR 46 is needed to feed the weight of the current arc to ALU 7.

The electronic model 31.l of the arc (Fig. 2) serves to simulate the lth arc of the digraph G, l = 1,2, ..., m.

Arc lock trigger 20.l serves to issue a blocking signal to re-select the corresponding arc during device operation.

The arc weight register 21.l and the arc lock register 22.l are designed to store the weight of the current arc and the zero code, respectively. Registers 21.l and 22.l have outputs with three states; transfer of the outputs to the third (high-impedance) state is provided by a single and zero signal at the resolution inputs (oe), respectively.

The first element And 38.l is necessary to form a signal of the presence of the lth arc in the graph.

The second element And 39.l is used to generate a select / block arc signal.

The element OR 40.l serves to combine the signals from the AND 39.l element and from the AND 33.l element.

The purpose of the elements of the minimum value block 58 is as follows.

The first 59 RAM of the ring cyclic system (MCC) is intended for storing the largest codes of values incident to the two selected vertices. They are arranged in descending order in accordance with (3).

The RAM 60 of the MCC cyclic fragment is required for storing codes of incident values to the selected vertex of the graph X.

, обрабатываемых в данный момент.The first 61 column counter is used to count the column numbers of the matrix.

currently being processed.

циклического фрагмента КЦС.The second 62 column counter is designed to count the column numbers of the matrix

cyclic fragment of MCC.

.The first 63 row counter is designed to count the processed rows of the matrix.

.

The second 64 column counter is used to count the number of the processed row of a circular MCC fragment.

The adder 65 minimum value is designed to sum up and obtain the minimum value of the intensity of accommodation in multiprocessor cubic cyclic systems with unidirectional transmission of information.

The first 66 element And serves to enable the work of the second 62 column counter with the supply of the corresponding pulse to its e-input.

The second 67 RAM of a ring cyclic system (MCC) is intended for storing the largest codes of values incident to the two selected vertices.

, обрабатываемых в данный момент ниже главной диагонали.The third 68 column counter of the adjacency matrix is used to count the column numbers of the matrix.

currently being processed below the main diagonal.

ниже главной диагонали.The second 69 row count is used to count the processed rows of the matrix.

below the main diagonal.

The first 70 and second 71 rows count is designed to count the number of rows in which non-zero values were detected.

The count 72 of the number of cyclic plots counts the number of processed cyclic fragments of the ring cyclic system.

The output 73 of the overflow of the counter 72 of the number of cyclic plots is intended for signaling the overflow of the counter 72 to the ECD, which is also a signal of the completion of operation of the device.

выше или ниже главной диагонали.SR-trigger 74 mode is designed to select the processing matrix

above or below the main diagonal.

The second element 76 And serves to combine the signals from the overflow output of the counter 70 and from the direct output of the trigger 23 mode.

The multiplier 77 is designed to calculate the distance value in accordance with the values of the distance matrix

Например, для

, значения вектора расстояний

соответствующие значениям матрицы

, упорядоченные по возрастанию имеют значения: 1,1,1,1.1, 2,2,2,2,3,3,3,4,4,5.The distance counter 78 serves to calculate the current distance value in accordance with the matrix value.

For example, for

, distance vector values

corresponding matrix values

sorted in ascending order: 1,1,1,1,1, 2,2,2,2,3,3,3,4,4,5.

The subtractive 79 counter is used to calculate the vector values of the same name

Consider the operation of the proposed device.

и начальное значение ноль («0…00»). В счетчике 79 содержится код значения

Initially, the counter 72 stores the zero code ("0 ... 00"), the codes of zero values are stored in RAM 59, 60, 64, 67. Codes 61 and 62 store unit codes (“0 ... 01). Counter 71 and 63 stores the value code of the unit (“0 ... 01”). Therefore, this value is fed to the address a1 input of RAM 59. Counter 64 stores the value code zero. The accumulator 65 stores the value code zero. At the second input of the element 66 And there is a zero potential from the overflow output of the counter 70. Because of this, there is zero potential at its output, which prohibits the operation of the counter 62. The counter 68 stores the value code one ("0 ... 01"). Counters 69 and 70 store the value codes of the unit. Therefore, at address a1-input of RAM 67 there is a code of value one. Counter 72 stores the value code zero. SR flip-flop 74 is in single state. This means that on its direct output there is a single potential, and on the reverse - zero. In the counter 79 is set the counting limit value

and the initial value is zero ("0 ... 00"). Counter 79 contains the value code

The proposed device is capable of solving the following tasks: placing unweighted graphs in a linear topological model, placing weighted graphs in a linear and ring model, and estimating the degree of closeness of the formed placement to the optimal one. Additionally, the proposed device allows to calculate the minimum value of the intensity of placement in multiprocessor cubic cyclic systems with unidirectional transmission of information according to the criterion of minimizing the intensity of interaction between processes and data.

The task of placing unweighted graphs with a topological model in the form of a ruler is solved in a device similar to the prototype. In this case, only the so-called “upper” part of the scheme, which includes EMG 31, registers 1 and 2, the group of elements OR 32.1 - 32.n, the group of elements AND 33.1 - 31.m, the block of elements OR 46, register 25, works element 26 comparison, one-shot 41, as well as BFP 3, block 4 permanent memory, BPLV 5, switch 6 and ALU 7.

. Одновременно в АЛУ 7 происходит и накопление суммарной длины связей L. Подсчет суммарной длины связей для текущего варианта размещения завершается, когда на выходе переполнения регистра 2 появляется сигнал переполнения. Одновременно этот же сигнал поступает на БФП 3, подготавливая его к формированию новой перестановки. Register 1 and register 2 sequentially select pairs of vertices as they arrive at the input 57 of the device. The signals of the selected pair of vertices pass through two corresponding elements of the group of elements OR 32.1 - 32.n and then form a single signal at the output of the corresponding element AND of group 33.1 - 33.m (say, element 33.l). A single signal from the AND 33.l element is fed to the OR 40.l element (arc models 31.l) and, getting further to the enabling input (oe) of the register 21.l, thereby allowing the appearance of data (weight of the lth arc) on the output of this register. Since the placed graph is unweighted, register 21.l contains either the code "00 ... 01" or the code "00 ... 00" (no arc). We will consider this code nonzero. The code "00 ... 01" from the output of the register 21.l enters the block of elements OR 46 and then through it - into ALU 7. At the same time, block 3 of the formation of permutations determines the selected vertices of the position, and ALU 7 generates a command for determining the distance between positions where the selected vertices of the graph should be placed. This distance is determined by the formula

. At the same time, the accumulation of the total length of the connections L is accumulated in ALU 7. The calculation of the total length of the connections for the current placement option is completed when the overflow signal appears at the output of the register 2 overflow. At the same time, the same signal arrives at BFP 3, preparing it for the formation of a new permutation.

Permutations are formed in the space-time form, that is, at each clock point in time, a single signal is initiated at only one (qth) output of the FBP 3, and their sequence determines the corresponding permutation. For example, a permutation (3 1 2) means that the first clock pulse appears at the second output of the FFT, the second at the third, the third at the first. In accordance with this, from the block 4 of the permanent memory (the binary codes of the position numbers are entered into the block 4 of the permanent memory), through the switch 6 in the ALU 7, the codes of the second position, the third and the first will be written off. This, in turn, means that the first vertex is placed in the second position, the second in the third and the third in the first. The best placement option is rewritten in block 5 and the corresponding value of the link length L is in register 25. The appearance of the signal at the signaling output of the BFP 3 indicates that all permutations are formed, and the best placement option is fixed in the BZLV 5.

The task of placing weighted and unweighted graphs in linear and / or ring topological models, as well as the task of assessing the degree of closeness of the formed placement to the optimal one, is solved in the prototype and therefore is not considered here.

The task of assessing the degree of closeness of the formed placement to the optimal one is solved as follows (in this case, only the “lower” part of the circuit works, including decoders 8 and 28, comparison element 17, counters 27, 9, 11, 12 and 13, memory block 10, registers 16, 25, 29 and 30, triggers 19, 23 and 24, multiplier 14, adder 15, subtractor 18, block of elements OR 36, elements AND 34, 35 and 37, elements 43, 44 and 45 of the delay and one-shot 42).

When a single signal appears at the signaling output of the BFP 3, the trigger 19 is set to one. A single signal from the direct output of the trigger 19 is supplied to the second inputs of the element 34 and the element 35. Since the mode trigger 23 is in the zero state, element 35 still remains closed and element 34 opens for the passage of clock pulses.

The first clock pulse passes through the element I 34, from where this pulse arrives at the counting input of the counter 27 and sets the leading edge to the value “00 ... 01”. The code from the output of the counter 27 is fed to the data input of the register 29 and to the input of the decoder 8, initiating the appearance of the unit at its first output. This unit is fed to the second input element And 39.1 (model 31.1). If a unit is present at the first input of element 39.1 (the trigger 20.1 is in the single state), then at the output of the element 39.1 a single arc selection signal appears. From the output of the element And 39.1, this signal passes through the element OR 40.1, arrives at the enabling input of register 21.1 and opens its output. As a result, the weight of the arc from register 21.1 passes through the block of elements OR 36, from where it gets to the first input of the comparison element 17, at the second input of which there is a code from the register 30 (initially "11 ... 1"). If the code from the block of elements OR 36 (the weight of the selected arc) is less than that already present in the register 30, a single signal is formed at the output of element 17. This single signal is fed to the first input of the element And 37 and provides the passage of a clock pulse from the element And 34, delayed by the element 44 of the delay. The impulse from AND 37 enters the synchronous inputs of register 29 and register 30 and records the value from the output of counter 27 (current arc number) and the weight code of the selected arc from block 36 (as the minimum at the moment), respectively, on the leading edge. In the case of the presence at the output of the element 17 zero, the element And 37 is blocked and therefore the pulse from the element 44 of the delay is not supplied to the synchronous inputs of the registers 29 and 30.

The next clock pulse similarly passes through the element And 34, again hits the counting input of counter 27 and increases the value of this counter to “00 ... 010”. From the output of counter 27, the code again hits the decoder 8, which causes the appearance of a unit at its second output. This unit is similarly supplied to the model 31.2 of the weighted arc, and from the second output of the weight of the arc of the model 31, the weight code of the second arc enters the block of elements OR 36. If such an arc exists, the corresponding code falls on the first input of the comparison element 17, to the second input of which the weight recorded in the previous steps comes from register 30. If the new weight is less than the previous one, then a single signal, indicating this, arrives at the first input of the element And 37 and passes a pulse through it from the element 44 of the delay. From the output of the And 37 element, the impulse goes back to the synchronous inputs of registers 29 and 30 and, at the front input, writes to register 30 a new arc weight (weight of the second arc), and to register 29 the counter value 27 is the arc number with the smallest weight at the moment.

This happens until an overflow signal (pulse) appears at the output of the overflow of counter 27, indicating that all arcs have been viewed and the least weight is contained in register 30, and the number of the corresponding arc is in register 29. At the same time, counter 27 is reset in the zero state, and the overflow signal simultaneously enters the recording input of the RAM block 10 to the delay element 43 and the first counting input of the counter 9. On the falling edge of the overflow signal, the counter 9 increases its value to “00 ... 01”. As a result, the minimum arc weight from register 30 is entered into block 10 of RAM at address “00 ... 01”. The overflow signal from counter 27 simultaneously enters the enable input of the decoder 28, ensuring that its output is selected depending on the code supplied from the output of register 29. The signal from the selected output of the decoder 28 (for example, l-th) is fed to the reset input of the flip-flop 20.l model 31.l, setting it to zero (blocking the l-th arc for the next device operation cycles is ensured). By that time, when the minimum arc weight is already recorded in the RAM block 10, the overflow signal from the output of the delay element 43 is fed to the installation (S) of the registers 29 and 30 and sets these registers to the initial state "11 ... 1". The current cycle of the device ends.

The next pulse passing through the element And 34, causes the device to work again according to the above algorithm. Register 30 maintains the smallest arc weight, excluding arcs blocked in previous cycles. When the decoder 8 selects an unblocked arc, the device operates as described above. When the decoder 8 selects an already blocked arc, the signal from the output of the decoder 8 does not pass through the AND 39.l element (zero is present at the direct output of the 20.l trigger). At the same time, the signal from the direct output 20.l trigger is supplied to the enabling input 22.l register. As a result, the zero code (recorded in this register from input 55.l) from the output of register 22.l goes through the block of elements OR 36 to the first input of the comparison element 17 and, being obviously less than any other code located in register 30, provides a zero signal at the exit of the element 17 and the blocking of the element 37.

When the overflow signal reappears on the counter 27, the value of the counter 9 increases to the code "00 ... 010". The overflow signal is fed to the write input of the RAM block 10 and writes there at the address “00 ... 010” the arc weight code from the register 30 output from the counter 9. Thus, the weights of the arcs of the graph G are sequentially recorded in ascending order of the corresponding values . This happens until counter 9 gives an overflow signal. This signal arrives at the installation S-input of the trigger 23, sets it to one and thereby allows the passage of clock pulses through the AND 35 element, prohibiting their passage through the AND 34 element. The counter 9 itself is reversibly transferred from the summing to the subtractive. From this moment begins the calculation of the minimum value of the intensity of placement in multiprocessor cubic cyclic systems with unidirectional transmission of information. The task of counting the minimum possible length L ^* is solved in the same way as in the prototype and therefore is not considered here.

The task of calculating the minimum value of the intensity of placement in multiprocessor cubic cyclic systems with unidirectional transmission of information is solved in the proposed device as follows.

Initially, in the same way as the principle described above, the “top” of the circuit “works out” so that in the memory block 10 there are arcs of the graph G, arranged in descending order of their weights. As can be seen from FIG. 4 when assigning arcs to the matrix system processors, first of all, the arcs with the highest weights should be assigned. Therefore, when selecting from block 10 of RAM, the first arc selected will be the arc with the largest weight value, and the last with the smallest value.

The next clock pulse from input 57 is fed to the e-input of counter 61, the counting input of counter 64 and the first input of element 66 I. In the counter 64, the content does not increase, because there is no single pulse at the e-input. Since the second input element 66 And there is no single signal, then a single pulse at its output does not appear.

Since the SR-flip-flop 74 is in a single state, the unit from its direct output did not receive the e-input of the counter 61, allowing its operation. Therefore, the clock pulse arrives at the counting input of the counter 61 and, on the leading edge, increases its contents by one, setting in it the code of two (“0 ... 010”).

и

по убыванию своих значений, а элементов матрицы

– по возрастанию. Элементы матрицы

и

уже расположены по убыванию своих значений в блоке 10 оперативной памяти.The search for the minimum value of the intensity of accommodation is supposed to order the elements of the matrix

and

descending their values, and matrix elements

- Ascending. Matrix elements

and

already arranged in descending order of their values in block 10 of RAM.

по возрастанию предназначены элементы 77, 78 и 79.To order the elements of the matrix

items 77, 78 and 79 are ascending.

. The value from the counter 78 is fed to the first input of the multiplier 77, but the second input of which contains the value from the block 10 of the RAM. At the same time, the value from the output of the counter 78 goes to the subtracting input of the counter 79 and reduces the value stored in it by one to one to the code

.

.This happens until an overflow signal appears at the counter overflow output, which is fed to the s-input of counter 78 and sets the count limit in it

.

The value from the output of the multiplier 77 is fed to the D-input of RAM 59 and 67, where it is stored at the address received at the A1 input and A2 input. After that, this value is fed to the corresponding second and third input of the adder 65, where it is fixed as an intermediate total value.

The next clock pulse is similarly fed to the counting input of the counter 61 and increases its content by one up to the three-way code (“0 ... 011”) on the leading edge. This code is fed to the a2 input of the RAM 59, on the a1 input of which there is a unit code from the output of the counter 63. As a result, the next code from the output of the multiplier 77 is sent to the D input of the RAM 59 for storage. Further, this code goes to the second input of the adder 65.

).This continues until the output of the overflow of counter 61 produces an overflow signal, which enters the counting input of counter 71 and increases its content by one up to the code of the two on the leading edge (the second row of the matrix is selected

).

выше главной диагонали обработана, а так как в нашем случае граф направленный, необходима обработка матрицы

ниже главной диагонали.Further, the operation of the circuit proceeds similarly, until a single impulse appears at the output of the overflow of the counter 71. This means that the matrix

above the main diagonal is processed, and since in our case the graph is directed, we need to process the matrix

below the main diagonal.

For this, a single pulse from the overflow output of the counter 71 is fed to the R input of the trigger 74, setting it to the zero state. thus, a zero potential appears on its direct output, and a single potential appears on the reverse.

Further, the operation of the circuit proceeds in the same way as the principle described above. The difference is that the intensity value comes from the output of the RAM 67 to the third input of the adder 65.

ниже главной диагонали просмотрена. Таким образом, множество основных процессоров

обработано. When a single potential appears at the output of the overflow of the counter 70, this means that the matrices

viewed below the main diagonal. Thus, many mainstream processors

processed.

At the last stage, processing of a set of cyclic fragments of a cubic system is necessary.

The overflow signal from the overflow output of the counter 70 is fed to the second input of the element 66 And to the e-input of the counter 72, allowing its operation.

Since there are N cyclic fragments, counter 72 counts the number of cyclic fragments processed.

A single impulse from the overflow output of counter 70 arrives at the second input of element AND 76 and sets the SR flip-flop 74 to one state, as well as to the second input of element 66 I. As a result, a single signal from the output of element 66 I enters the e-inputs of counters 62 and 64, permitting their work.

. Обработка очередного циклического фрагмента заканчивается, когда на выходе переполнения счетчика 64 появляется единичный потенциал, который поступает на счетный вход счетчика 72, увеличивая его содержимое по переднему фронту на единицу.Further, the operation of the circuit is similar to the principle described above. The difference is that the D-input of RAM 60 receives the values from the matrix

. The processing of the next cyclic fragment ends when a single potential appears at the output of the overflow of the counter 64, which arrives at the counting input of the counter 72, increasing its content along the leading edge by one.

The next code from the output of the RAM 60 is fed to the first input of the adder 65.

The appearance of a single pulse at the output of the overflow of the counter 72 means that all cyclic fragments of the ring cyclic system are processed. A single impulse from the output of the overflow of the counter 72 arrives at the output 73 of the overflow of the device, from where it enters the ECD to decide on further actions of the circuit.

At this time, the minimum value of the intensity of placement in multiprocessor cubic cyclic systems with unidirectional information transfer comes from the output of the adder 65 to the VUU for making decisions about further actions.

Thus, the proposed device, similar to the prototype, allows forming the optimal placement of unweighted graphs in a linear topological model. It is possible to place weighted graphs in the device, and it is possible to choose two models of the layout area - linear or circular. The found suboptimal placement is compared with the limiting option by counting and comparing the values of the bond lengths L and L ^* . Additionally, the proposed device allows to calculate the minimum value of the intensity of placement in multiprocessor cubic cyclic systems with unidirectional transmission of information according to the criterion of minimizing the intensity of interaction between processes and data.

Claims (2)

1. A device for calculating the minimum value of the intensity of placement in multiprocessor cubic cyclic systems with unidirectional information transfer, containing the first shift register, the second shift register, permutation generation unit (BFP), permanent memory unit, memory unit of the best variant (BLP), switchboard, ALU , decoder arc selection, reversible cell counter, memory block, topology counter, first and second distance counters, multiplier, adder, register of the minimum bond length, first comparison element, subtractor, start of account trigger, mode trigger, topology setting trigger, link length register, second comparison element, arc counter, arc lock decoder, arc number register, minimum weight register, electronic graph model, groups 1 through n th elements OR, a group of 1st to m th elements AND, the first and second elements AND, the second block of elements OR, the third element AND, the first and second one-shot, the first, second and third delay elements, the first block of elements OR, and outputs BFP connected to the corresponding input by the fixed memory unit and the corresponding BZLV inputs, the signaling output of the FPU is connected to the setup input of the start of the counting trigger, the outputs of the permanent memory unit are connected to the corresponding inputs of the switch, the output of which is connected to the input of the ALU, the output of which is connected to the information input of the BPU, and the output of the BPUF is connected to the first information input of the ALU, the overflow output of the first shift register is connected to the input of the second shift register; the outputs of the first and second shift registers from the first to the nth are connected to the first and second eye inputs of the elements OR 1 st to n-th, respectively, the output of the shift register overflow is connected to the control input of the ALU and the control input of the BFU, the clock input of the device is connected to the input of the shift register, with the clock input of the BFP and with the first inputs of the first and second elements AND , the output of the arc counter is connected to the input of the arc select decoder and the data input of the arc number register, the output of the block of elements OR is connected to the first input of the first comparison element and to the data input of the minimum weight register, the output of the minimum weight register En with the second input of the first comparison element and with the data input of the RAM block, the output of the first delay element is connected to the minimum weight register setting input and the arc number register setting input, the third AND output element is connected to the minimum weight register synchronous input and the arc number register synchronous input , the output of the arc number register is connected to the information input of the arc lock decoder, the overflow output of the arc counter is connected to the enable input of the arc lock decoder, as well as to the input of the first arc the delay element, the first counting input of the reversible cell counter and the write input of the RAM block, the output of the first element I is connected to the counting input of the arc counter and the input of the second delay element whose output is connected to the second input of the third element I, the first input of which is connected to the output of the element comparison, the second input of the first element And is connected to the direct output of the trigger trigger count, which is also connected to the second input of the second element And, the third input of the first element And is connected to the inverse output of the trigger mode mode, the direct output of which is connected to the third input of the second element, And the output of the second element, And connected to the second counting input of the reversing cell counter, the output of which is connected to the address input of the RAM block whose output is connected to the first input of the multiplier, the output of the second distance counter to the second input of the multiplier, the output of which is connected to the first input of the adder, the second input of which is connected to the output of the register of the minimum bond length and to the second input of the subtractor, the output of the adder The input to the data register of the minimum connection length, the output of the third delay element is connected to the synchronous input of the register of the minimum connection length, the output of the second element And the counting input of the first distance counter is connected to the input of the third delay element, the output of the second one-vibrator is connected to the synchronous input of the distance counter, the overflow output of which connected to the counting inputs of the topology counter, the second distance counter and to the input of the second one-shot, the output of the topology counter is connected to the input of the distance counter, input The device data is connected to the data input of the topology counter, the synchronization input of the topology counter is connected to the device installation input, the direct output of the topology set trigger is connected to the enable input of the topology counter, the installation input of the topology set trigger is connected to the device installation input, the reset input of the topology set trigger is connected to the input device installation, the output of the overflow counter of the cell counter is connected to the setup input of the mode trigger, the reset input of which is connected to the installation input the device, the output of the link length register is connected to the second input of the second comparison element and to the first input of the subtractor, the first input of the comparison element is connected to the output of the ALU and the data input of the link length register, the output of the first one-vibrator is connected to the synchronous input of the link length register, the reset input of the account trigger is connected to the device installation input, the lth output of the arc selection decoder (l = 1, 2, ..., m) is connected to the lth input of the arc selection of the electronic model of the graph, the lth output of the arc lock decoder connected to the lth input of the arc lockthe electronic model of the graph, the lth output of the arc weight of the electronic model of the graph is connected to the lth input of the second block of elements OR and the lth input of the first block of elements OR, the lth output of the element AND of the group of elements AND from the 1st to the mth connected to the lth control input of the electronic model of the graph, the output of the block of elements OR is connected to the second information input of the ALU, the output of the second comparison element is connected to the input of the first one-vibrator, the outputs of the elements from the 1st to the nth OR are connected to the corresponding inputs of the elements AND 1 th on the m-th, the output of the subtractor is connected to the output d device connection lines, characterized in that it additionally introduces a minimum value block containing the first RAM of the ring cyclic system, the cyclic fragment RAM, the first column counter, the second column counter, the first row counter, the second column counter, the minimum value adder, the first And element , the second RAM of the ring cyclic system, the third counter of the columns of the adjacency matrix, the second row counter, the first and second rows number counter, the count of the number of cyclic sections, SR-mode trigger, WTO the second element And, the multiplier, the distance counter, the subtracting counter, the output of the RAM block is connected to the first input of the second element And, the second input of which is connected to the overflow output of the first counter of the number of lines, the second input of the first 66 I element and to the e-input of the number counter cyclic plots, the counting input of which is connected to the overflow output of the second column counter, the e-input of which is connected to the output of the first element I, and to the e-input of the second column counter, the output of which overflow is connected to the counting input of the second column counter, the output of which is connected to the a1 input of a cyclic fragment RAM, a2 input of which is connected to the output of the second column counter, the counting input of which is connected to the clock input of the device, the counting input of the distance counter connected to the clock input of the device, the output of the distance counter connected to the first input of the multiplier and to the counting input of the subtracting counter, the overflow output of which is connected to the s-input of the distance counter, the second input of the multiplier is connected to the output of the operational unit In this case, the output of the second element I is connected to the S-input of the SR-mode trigger, the R-input of which is connected to the overflow output of the second counter of the number of rows, the counting input of which is connected to the overflow output of the first column counter, the e-input of which is connected to the direct output SR- trigger mode, the reverse output of which is connected to the e-input of the third column counter, the counting input of which is connected to the clock input of the device, the counting input of the counter of the first column counter and to the s-inputs of the first RAM of the ring cyclic system and the second The RAM of the ring cyclic system, the D-input of which is connected to the output of the multiplier and the D-input of the first RAM of the ring cyclic system, the A1-input of which is connected to the output of the first row counter, a2-input of the first RAM of the ring cyclic system, is connected to the output of the first column counter, A1-input of the second RAM of the ring cyclic system is connected to the output of the second line counter, the counting input of which is connected to the output of the first counter of the number of lines, D-input of the RAM of the cyclic fragment is connected to the output of the RAM block, the RAM of the cyclic fragment is connected to the first input of the adder, the second and third inputs of the adder are connected to the outputs of the first RAM of the ring cyclic system and the second RAM of the ring cyclic system, the output of the adder is connected to the output of the VUU, where the decision on further actions of the multiprocessor cubic cyclic system, the output the overflow counter of the number of cyclic sections is connected to the output of the overflow device. 2. The device according to claim 1, characterized in that the electronic model of the graph contains m electronic models of the arc, and the l-th electronic model of the arc (l = 1, 2, ..., m) contains the arc lock trigger, the arc weight register, the lock register arc, the first element is AND, the second element is AND, element OR, and the inputs of the first element AND are connected to the corresponding inputs of the device graph, the output of the first element AND is connected to the synchronous input of the arc weight register and to the installation input of the arc lock trigger, the reset input of which is connected to l entrance blocking arcs and the electronic model of the graph, the input data of the arc weight register is connected to the lth input of the arc weight of the device, the first input of the OR element is connected to the lth control input of the electronic model of the graph, and the second input of the OR element is connected to the output of the second AND element, the first input of which connected to the direct output of the arc lock trigger and to the enable input of the arc lock register, the second input of the second element I is connected to the lth arc selection input of the electronic model of the graph, the reset input of the arc lock register is connected to the lth device reset input, output The d register of the arc lock is connected to the lth output of the arc weight of the electronic model of the graph, which is also connected to the output of the arc weight register, the output of the OR element is connected to the enable input of the arc weight register.

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