SU1496022A1 - Redundant clock pulse generator - Google Patents

Abstract

The invention relates to a pulse technique and can be used in redundant generators, the formation of the output signals of which is carried out synchronously. The purpose of the invention is to improve the accuracy of the formation of output signals. To achieve this goal, an element OR 2 and a differentiator unit 7 are introduced into each pulse shaping channel 1 of a redundant clock pulse generator. Each pulse shaping channel also contains a master oscillator 8, a pulse counter 3, a majority element 4, a trigger 5 and a delay element 6. The operation of the former is explained in the timing diagrams provided in the specification. 2 Il.

Description

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The invention relates to a pulse technique and can be used in redundant generators, the formation of the output signals of which is performed synchronously.

The aim of the invention is to increase the accuracy of the formation of output signals.

FIG. 1 shows a functional diagram of a redundant path impulse generator; in fig. 2 - time diagrams that show his work.

The device contains clock generation channels, each of which includes an OR 2 element, a 3-pulse counter, a major element A (on 2N + 1 inputs), a trigger 5, a delay element 6, a differentiating unit 7 and a master oscillator 8.

In each channel IjN + f, the master oscillator 8, the element OR 2, the counter of 3 pulses, the majority element 4, the trigger 5, the delay element 6 and the differentiating unit 7 are connected in series. The output of the counter of 3 pulses is connected to the second input of the element OR 2, and the output of the differentiator unit 7 is connected to the input of the zero pulse counter 3. The output of the counter 3 pulses of the first channel is connected to the first inputs of the major elements 4 of all channels, the output of the counter 3 pulses of the second channel C - to the second inputs of the majority elements 4 of all channels, the output of the counter 3 pulses of the channel

connected to (2K + 1) th inputs /

tare elements 4 all channels.

The shaper works as follows.

Consider the operation of the device, provided that it contains three channels (N 1). Suppose that the master oscillators of the first, second and third channels have the frequency of the signals, respectively, f (FIG. 2a), fi (cnig.2b and fj (figv), f, 7fj7 f,

Let it be required to obtain a sequence of clock pulses with a repetition rate K times less than the frequency of the master oscillator (for example, four times, i.e. K 4). In this case, the number of bits in counter 3 is chosen to be three (one in the highest bit, appears after four pulses have passed).

Suppose that, at the Starting Time, the counters of 3 pulses that drive the generators 8 and the triggers 5 of all the channels were in the zero state. At time t, (fig.2g), the most significant bit of the pulse counter 3 of the first channel changes its state, and its output signal (high level) prohibits the passage of pulses from the output of the master oscillator 8 through the element OR 2 to the input of the counter 3 pulses of this channel and fed to the first inputs of the majority element 4 of all channels.

At time t, (figd) the most significant bit of the counter 3 pulses of the second channel 1 changes its state, and its output signal (high level) prohibits the passage of pulses from the master output (e generator 8 through the OR 2 element to the input of the counter 3 of this channel is fed to the second inputs of the majority elements of all channels 4. At the same time, the majority elements 4 change (fig.2l, m, n) and triggers 5 (fig.2p, p, c) of all channels. The output signal of the counter of 3 pulses of the third channel does not change its state (Fig. 2e).

The output signal of the trigger 5 of each channel is fed to the delay element 6 and after a time i ,, determined by this element (fig.2m), the differentiating blocks 7 of each channel form pulses of duration S g (fig.2j, and k), which are fed to input zeroing. counter 3 corresponding channel. Next, the process of forming the clock pulses is repeated.

As follows from the description of the functional diagram of the device (Fig. 1) and the timing diagrams (Fig. 2), the duration of the output clock pulses is determined by the delay time {, element: 6 delay, and the follow-up period T of the pulses is equal to l / K-fj, where K is the predetermined division factor of the counter of 3 pulses (in this case K 4); fg is the frequency of the trace of the impulses of the master oscillator 8 of the second channel (f is the average of the frequencies ff. fi. fa).

If the redundant clock pulse shaper contains 2N + 1 channels, then the wire is similar

reasoning, it can be concluded that the output signals of all the tapes vary synchronously with the repetition period Tj l / K-f, 4, where f N +, is the average of the frequencies f, fj, f,, and the duration of the pulses with s.

Claims (1)

Invention Formula A redundant clock pulse generator containing 2N + 1 pulse shaping channels, each of which includes a generator, pulse counter, major element, trigger and hold element, with the same name inputs 96022 majority e-lemrites of all channels of impulse formation are interconnected, about tl and ch and n In order to increase accuracy Formations, B, each pulse shaping channel are introduced the OR elements and the differentiating unit, and in each JO pulse formation channel, the master, generator, OR element, pulse counter, majority element, trigger, delay element and differentiating unit are connected, the output of which is 15 To the input of the zeroing pulse counter, the output of which is connected to the second input of the OR element. a s i g 9 e Well at to / I m n but f with