SU1429301A2 - Pulse train shaper - Google Patents

Abstract

The invention relates to a pulse technique and can be used in breathing electrostimulators. The purpose of the invention is to expand the functionality of the former. The shaper contains a pulse generator, a divider 2 frequencies, counters 3 and 4, a group of 5 elements AND, a comparison unit 6, a conversion unit 7, executed, for example, in the form of a Johnson counter, and an element 8. Introduction of a comparison unit 10, counters 9 and 11 , the frequency divider 13, the inverter 12 and the formation of new functional connections allow, at the output of the shaper, to form bursts of pulses with a linear-step increase in the frequency and duration of the pulses in the first half of the pack and the maximum frequency and duration of the pulses half a pack. 1 il. about 9

Description

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The invention relates to a pulse technique, can be used; in the field of medical technology, in h | tnosti in lectopulators of smoke | 1Ni and is an improvement of the invention according to the author. No. 1396249.

The aim of the invention is to extend the functionality of the g & the account of the formation of the linear step- 4jaToro of the change in the duration of the pulses in the packet while maintaining the linear. step change of the hour of the pulse following in the pack.

j The drawing shows a structural diagram of an impulse packer.

; The pulse trainer will contain a pulse generator 1, a division of 2 frequencies, counters 3 and 4, a group of 5 And elements, a block of 6 comparisons, Lok 7 of recalculation, fulfilled, for example, in the form of a Johnson counter, an element of And 8, counter 9, comparison unit 10, counter 11, inverter 12, de Litel 13 frequencies, trigger 14, output bus 15. The output of the pulse generator 1 is connected to the subtracting input of counter 4 and the input of the split cell divider 2, the output of which is connected to the counter addition input 9 and the addition input of the counter 3, whose codes are connected to the first inputs of group 5 element And, the second inputs of which are interconnected, with the nth discharge of the counter 3 by the input of the inverter 12 and the input of the conversion unit 7, the output of which is connected to the first input of the And 8 element, the second 8HSD of which is connected to the installation input of the counter 4 and the output of the block - ya b comparison, the first group of inputs of which are connected respectively to the outputs of the group -5 elements I, and the second group of inputs connected to the outputs of the counter 4, the input of which readout is connected to the addition input of the counter a I, the outputs of which are connected to the first m inputs of the unit 10 of comparison the second g the ruppe of the inputs of which are connected, respectively: (p-1) of the inputs to the outputs of counter 9, the p-th input to the output of inverter 12 and the reset input of the counter 9, (g-n) inputs to the logical bus O, and the output of the comparison unit 10 is connected to the installation the input of the counter 11 and the clock input of the trigger 14, the information input of which is connected to the output of the frequency divider 13, the input of which is connected to the output of the And 8 element.

. Shaper packs pulses works as follows.

The generator 1 generates a sequence of pulses of the reference frequency, which is fed to the input of the counter 10 reading 4 and the addition input of the counter 11 directly, and to the summing inputs h: the cheaters 3 and 9 through the divider 2 frequencies.

When logical 1 on the n-th bit

15 counter 3, the code at the outputs of group 5 of the elements And corresponds to the code at the outputs of counter 3, and for logical o, at the nth digit of counter 3, the outputs of group 5 of the elements of AND are

0 E state of logical O regardless of the code at the outputs of the counter 3. The codes at the outputs of the group 5 of the elements I. are compared with the codes of the counter 4 by the block 6 of comparison and with the coincidence

5 codes at the output of the comparison block a logical 1 appears, which, by the installation input of the counter 4, sets the initial code at its outputs, and the output of the comparison block 6 returns to the outcome | the 1st state of the logical 0, thereby forgiving a positive impulse. The following coincidence of the codes on the outputs of the group of 5 elements And and the outputs of the counter 4 causes

The effect at the outputs of block 6 is the comparison of the next positive pulse, etc.

I

In the process, the code on the outputs

0 of counter 3 is increased, and the code at the outputs of counter 4 is reduced, the rate-of-change of codes for each counter is constant, and the ratio of their speeds is determined by the division factor of the splitter 2 frequency. As a result, a sequence of pulses with frequency, is formed at the output of the comparison block at logical 1 at the nth discharge of counter 3.

- linearly variable law. For a logical O on the pth discharge of the counter, 3 the code on the outputs of the 5-circuit 5 elements And is O, therefore the number of pulses required

e to the input of the subtraction counter 4 for

its zeroing is constant and equal to the minimum value, which corresponds to the maximum frequency at the output of the reference block b.

The recalculation unit 7 forms a pulse sequence, the duration of which is equal to the period of operation of counter 3, and the pause between pulses is a multiple of this period.

At the output of the element I, 8. bursts of pulses are formed, and the frequency of the pulses following in the first half of the batch increases according to a linear-step law, and in the second half the frequency is constant and equal to the maximum value.

The process of generating signals at the output of comparator unit 10 is as follows. When logical 1, at the nth digit of counter 3, the inverter 12 sends a logical signal O to the reset input of counter 9 and enables it to work. When the codes on the first and second lines of inputs at the output of the comparison unit 10 are compared, pulses are generated linearly -step law, since the number of pulses required for the input of the summation of the counter 11 increases with the code at the outputs of the counter 9. For a logical O in the nth digit

through the frequency divider 13, which lowers the frequency of the emulsions to the required value, always lower than the frequency at the clock input. At the trigger output, pulses are formed, the frequency of which is determined by the frequency on the information input, and the duration is equal to the period of the ff pulses. Thus, at the output of the device, a burst of pulses with a linear-step increase in the frequency and duration of the pulses in the first half of -15 packs and m maximal, the frequency and duration of the pulses in the second half of the pack are formed.

Claims (1)

Invention Formula 20 Shaper packs pulses auth. St. No. 1396249, characterized in that, in order to expand its functionality, a second comparison unit, 25 third and fourth counters, a second frequency divider, an inverter and a trigger are introduced into it, the output of the n-th bit of the second counter being connected via an inverter the reset input of the third counter, counter 3, the code on the second group of which the summation input is connected The doses of the comparator unit 10 are determined by the nth digit equal to 1, therefore the number of pulses required at the addition input of counter-11 to match the codes is constant and equal to the maximum value, which corresponds to the minimum frequency at the output of the comparative unit 10. Trigger 14 fulfills the function of the output pulse generator. A pulse sequence is supplied to its clock input from the output of the comparator unit 10, the frequency of which decreases according to a linear-step law with a logic at the nth discharge of counter 3 or remains minimal with a logic O at the nth discharge of counter 3. At the information input bundles of impulses are supplied from the output of the element And 8 35 to the output of the first frequency divider, and the vpdsody are connected respectively to (p-1) inputs of the first input group of the second comparison unit, in which the pth input is connected to the output of the inverter, (mn) inputs are connected to the logical bus O, and m inputs of the second group the inputs of the second comparison unit are connected respectively to the outputs of the fourth counter, the summation input of which is connected to the output of the pulse generator, and the setup input is connected to the output of the second comparison unit and the trigger input of the trigger, the output of which is connected to the output bus, and nformatsionny input coupled to an output of the second frequency divider having an input connected to the output member I. 45 9301 through the frequency divider 13, which lowers the frequency of the emulsions to the required value, always lower than the frequency at the clock input. At the trigger output, pulses are generated, the frequency of which is determined by the frequency on the information input, and the duration is equal to the period of the switching pulses. Thus, at the output of the device, a burst of pulses is formed with a linearly stepwise increase in the frequency and duration of the pulses in the first half of the pack and m.maximum, the frequency and duration of the pulses in the second half of the pack. Invention Formula Shaper packs pulses auth. St. No. 1396249, characterized in that, in order to expand the functionality, a second comparison unit, third and fourth counters, a second frequency divider, an inverter and a trigger are introduced into it, the output of the n-th bit of the second counter being connected via an inverter five to the output of the first frequency divider, and the vpdsody are connected respectively to (p-1) inputs of the first input group of the second comparison unit, in which the pth input is connected to the output of the inverter, (mn) inputs are connected to the logical bus O, and m inputs of the second group the inputs of the second comparison unit are connected respectively to the outputs of the fourth counter, the summation input of which is connected to the output of the pulse generator, and the setup input is connected to the output of the second comparison unit and the clock input of the trigger, the output of which is connected to the output bus, and The information input is connected to the output of the second frequency divider, the input of which is connected to the output of element I. five