SU1312729A1 - Multichannel detector of maximum amplitude - Google Patents

Abstract

The invention relates to a pulse technique and can be used in telecommunications, radio engineering, as well as various information processing systems for extracting signals with a maximum amplitude in a group of N independent channels. The purpose of the invention is to expand the functionality of the device. This is achieved by providing an additional selection of N independent signals, each of which is equal to the maximum of all previous signal samples in the i-th channel. The device contains a pulse generator 1, a counter 2, a switch 3, a comparator 4, a transponder key 5, a mode setting input 9, device inputs 10-110-N. To achieve this goal, the driver control signal generator 6, the multi-bit delay line 7 and the second key 8 are added to the device. In this case, pa each output of the first key 5 will contain N signals each of which will be equal to the maximum of all previous counts of any one of the channels. I il. “; oo k5 th cd

Description

And: and) shaving refers to a pulse technique and can be used in telecommunications, radio engineering, and also in various information processing systems for extracting signals with a maximum amplitude in a group of N independent channels.

The aim of the invention is to incorporate the functionality of the device by providing an additional allocation of N independent signals, each of which is equal to the maximum of all the previous signal samples in the i-th channel.

The drawing shows a functional diagram of the proposed device.

The device contains a pulse generator 1, a counter 2, a switch 3, a comparator 4. the first key 5, shaper 6 iHK iHK) nuix and iivipulses, multi-bit .1IIPS 7 delay, second key H, input 9 vcTiiHoBKH mode, inputs 10 1 - 10 -N (U |, j. U ;.) device.

The output of the pulse generator 1 is connected to the input of the counter 2, the outputs of which () are connected to the control inputs of the commutator)) 3. The output of the switch 3 is connected to the ne () input of the comparator 4, the input of which is connected to the output of the second key 8.

11n (}) the key inputs of the key 8 are connected respectively to the exit of the nerve and 1 () with, one week |.) Cell of the delay line 7. And | 1 (|) () the input inputs) 1 of the first key,) are connected respectively to the output of the commutator) and the output of the second key 8. Unrav, 1 k) The first input of the first key 5 is connected to B1,1 comparator 4 input The output of the first k, 1K) cha D) is connected to the information input, 1 of line 7 of the delay, corrected by BX (j- .1Ы K () T () oii С {X dinin1 with the outputs of the former D) pack | 1av. 1 single signal. The output of the pulse generator 1 is connected to the input 4) (.), 1I (.

Key start 5 is the output of poiicTBa, and inputs 10-1 through 10-N (U |, U, ..., 17.,) are inputs to the device.

, The device can operate in two modes.

The clock pulses of the pulse generator 1 pulses are cyclically counted by counter 2, the output signal of which in the form of a K-bit d-binary code controls the sequential, first connection of each of the N input signals U | and through switch 3

at the first input of the comparator 4.

If the sigpal (“O or“ 1), fed to y111) by sending the key 8 input from the mode setting input 9, connects the first cell of the delay line 7 to the output cnrna.ia output, then the device operates in the single maximum selection mode from N independent input signals.

The operation of the device in the case occurs in the following way.

Let in the initial m state (during the first cycle) the output signal of key 8 is zero, and the signal of the first channel passes to the output of switch 3. Comparison of these signals in comparator 4 leads to its triggering, with this. At the output of comparator 4, a high level of signal appears, the output of switch 5 to the output of switch 5 is the output signal of switch 3.

Thus, in the first clock at the output of the key 5, but in; 1, the signal that passes in the second clock to the output of the first cell of the delay line 7 and through the key 8 to the second input of the comparator 4. Simultaneously to the first input of the comparator 4 from the output switch 3 receives a second channel signal.

If the signal is higher than the signal received in the previous cycle on the first channel} and which, due to the presence of the delay line 7, is fed to the second input of the computer | ator 4, then the comparator 4 will also work in this cycle, the second channel. If the signal of the third channel of the channel, connected to the output of the switch () |) and 3 in the third cycle of the minor channel of the sig5 na.ia, is not received on the second channel, and which in the third cycle is present at the start of the key 8, the comparator 4 is not work- I aiM. ei4) the output signal has a low uro luMib. which again provides the passage of the signal of the second channel to the output of the key o and its rewriting in the first cell of the delay line 7.

Thus, on bb) 1 key input 5, every time there is a signal equal to the maximum of the signals of all N channels, from 1 to 1 on (x) switch 3

5 in all the wrong bars.

c, 1 and the signal applied to the control; 1 is the input of the key 8 from the mode setting input 9, provides a sub-switch to its output for the signal of the last (N-th) cell. 1ININ 7 delay, the device operates in the mode of separate selection of the maximum 1 values but for each of the N channels.

The operation of the device in this case is as follows.

5 Let the output signal of the Nth cell of the delay line 7 and the output signal of the key 8 during the nerve N clock cycles be zero, and the signals of an arbitrary i-ro channel pass to the output of the switch 3 during the clock cycles i –f nN, where n O, 1, 2 on the left of the signal of the i-ro channel in the i-th cycle will in this case trigger the comparator 4, since the output signal of the key 8 in the iM cycle is zero. The high level of the signal at the output of the comparator 4 ensures the passage of the signal

5 i-ro channel via key 5 to the input line 7 delay. The next readout of the i-ro channel signal appears on the output of switch 3 in the (i 4 N) -M cycle, and this is exactly what

Those at the output of the Nth cell of the delay line 7 and at the output of the key 8 a previous sample of the i-ro channel signal appears, since the delay line 7 shifts the input signals by N clock cycles.

If the output signal of the switch 3 in the (i - | - N) -M cycle is greater than the previous reference signal of the i-ro channel from the output of the key 8 to the second input of the comparator 4, then the output of the comparator 4 in the (i + N) -M cycle also a high signal level that transmits the i-ro signal in the (1 + N) -M cycle through key 5 to the input of delay line 7. If the signal readout in the next (i - | - 2N) -M cycle is less than the maximum of the previous channel samples arriving in (i - (- 2N) -M cycle from the output of the key 8 to the input of the comparator 4, then at the output of the comparator 4 the low level of the signal that passes at the output of the key 5 is not the output signal of the switch 3 in the (i - | - 2N) -M cycle, but the output signal of the key 8, i.e. the maximum of all passed samples is still fed to the delay line 7 i-ro channel.

Thus, at the output of key 5 in each cycle of N clock cycles there are N signals, each of which is equal to the maximum of all previous samples of any one channel.

Claims (1)

Invention Formula A multichannel maximum amplitude detector containing a pulse generator connected in series and a counter, the outputs of which are connected to the control inputs of the switch, whose information inputs are the device inputs, and the output connected to the first input of a commander connected to the first key, characterized by that, in order to extend the functionality by providing additional allocation of independent signals, each of which is equal to the maximum of all ETS signal samples in the i-th channel, administered generator control signals multibit bottom delay line and the second key information inputs of which are connected to the outputs of the first and last cell line 0 of the delay connected by the information inputs with the output of the first key, which is the output of the device, and the control inputs are connected to the outputs of the control driver, the input of which 5 is connected to the output of the pulse generator, the outputs of the switch and the second key are connected to the information inputs of the first key, the output of the second key is also connected to the second input of the comparator.