SU1451842A2 - Shaper of pulse trains with variable pulse recurrence rate in train - Google Patents

Abstract

The invention relates to a pulse technique and can be used in information analysis and processing systems, in frequency shaping devices, for example, when necessary, to modulate an information signal according to a certain law, and is an improvement of the device according to the author. No. 1215165. The purpose of the invention is to expand the functionality by providing a continuous periodic pulse sequence with a linear-step change in the pulse frequency according to a triangular law. To achieve this goal, an HE 6 element, a pulse shaper 7 and an output bus 16 are introduced into the pulse generator with a varying pulse frequency in the stack. The shaper also contains memory counter registers 1, 2, frequency divider 3, comparison unit 4, element And 5, the bus 14 reference frequency and the output bus 15. 1 Il. with (L

Description

at the output, the initial code, depending on h, generates a pulse, which after the code on its D-inputs. At the same time, the output of the comparison unit 4 is set to the logical O. state. The next match, the code on the bit, outputs the installation input and sets the logical 1 to the output of the counter-register 2 memory (on the D-inputs of the counter-register 2 - level 1) .

dah counters-registers 1,2 causes 15 the described process of forming the impulse at the output of the unit 4 comparing the next positive pulse, etc. Since the Hi code of the discharge outputs of the counter-register 1 is increased, the time for which the sequential pulse sequence

The code changes at the bit outputs of the counter-register 2 of the memory from the initial state up to the moment of coincidence with the code at the bit outputs of the counter-register 1 memory, increases and increases from one to the other, i.e. the pulse frequency at the output of comparison unit 4 decreases from pulse to pulse linearly, since the rates of change of codes on the bit outputs of the counter-registers 1,2 of memory are constant. At the moment of time when the output of the most significant bit of the counter-register 1 of the memory is at logical level 1, the driver 7 of the pulses produces a pulse that goes to the installation

Shaper packs of pulses with varying pulse frequency in a pack according to auth.St. No. 1215165 characterized in that, in order to expand the functional

the input and writes to the output of the counter-register 2 memory a logic level of 40 possibilities; an additional output bus, the item NOT, are entered into it. and a pulse shaper, the first input of which is connected to the high-order output of the first counter — 45 of the memory register and through the element {t NOT — to the D-inputs and the input of the second counter-memory register, the setting input of which is connected to the output of the pulse shaper, second input 50

O (at the O-inputs of counter-register 2 is level O). Now each pulse arriving at the counting input of counter-register 2 of memory causes a decrease in the code at its output i (Ha logical O is present at the mode input). Time, for which the second, the code changes on the bit outputs of the counter-register 2 of the memory from the initial state to the moment of coincidence

which is connected to the output of the comparison unit and an additional output bus.

with the code on the bit outputs of the counter-register 1 of the memory, decreases and

the pulse sequence is repeated.

Thus, in this device a continuous period is formed.

0

five

With a linear-step change both upwards and downwards, the pulse frequency is reduced. The frequency change period is adjusted by changing the division factor of the 3 frequency divider. At the same time, the minimum and maximum pulse frequency in the sequence retain their values, since they do not depend on the division factor of the 3 frequency divider.

Claims (1)

Invention Formula Shaper packs of pulses with varying pulse frequency in a pack according to auth.St. No. 1215165, characterized in that, in order to expand the functional 0 possibilities, an additional output bus is entered into it, the item is NOT. and a pulse shaper, the first input of which is connected to the high-order output of the first counter — 5 of the memory register and through the element {t NOT — to the D-inputs and the input of the second counter-memory register, the setting input of which is connected to the output of the pulse shaper second entrance Opportunities, an additional output bus, an NOT element and a pulse shaper are entered into it, the first input of which is connected to the output of the higher bit of the first counter-register of the memory and through the element {t NOT to the D-inputs and the input of the second counter-register of the memory , the installation input of which is connected to the output of the pulse former, the second input which is connected to the output of the comparison unit and an additional output bus.