SU1486984A1 - Controller - Google Patents

Description

The invention relates to automation and can be used to build high-precision control systems. The purpose of the invention is to improve the accuracy of control. The output signals of the sensor unit 21 and the task unit 1 are sequentially subjected to mathematical processing using an adder 5, an integrator 6 and a logic circuit, and a periodic signal from the output of the filter 15 arrives at the integrator's input. As a result, control actions are formed with a small dynamic error and without using a universal calculator . 1 il.

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1486984

The invention relates to automation and can be used to scale the control signals and signals of external information and the formation of control actions on them.

The purpose of the invention is to improve the accuracy of control.

The drawing shows a functional diagram of the regulator.

The regulator contains a block 1 of the job, the first source 2 of the reference voltage, multiplexer 3, inverter repeater 4, adder 5, integrator 6, zero detector 7, £> trigger 8, accumulating adder 9, block 10 registers, digital-to-analog converter 11, generator 12 pulses, the first counter 13, the second counter 14, the filter 15, the distributor 16 pulses, the first 17 and the second 18 delay elements, the second source 19 of the reference voltage and the control circuit 20. The input of the regulator is connected to the output of the block of 21 sensors, and the output of the regulator is connected to the input of the block of 22 torque sensors.

The regulator works as follows.

Information from the sensor unit 21 of the task unit 1 and the output voltage of the source 2 are periodically fed to the outputs of multiplexer 3 according to a given program. The sum of the output voltage of the multiplexer 3, the inverter inverter 4 and the filter 15 (square wave without a constant component) is fed to the integrator 6. The amplitude of the output voltage of the filter 15 is constant (this is achieved by powering the counter 13 from the source 19) and exceeds the sum of the voltage modules on the first and second outputs multiplexer 3. As a result, the output voltage of the integrator 6 periodically passes through zero, changing the state of the detector 7 and, at the moment of receipt of the next pulse from the generator 12, trigger 8, which controls the direction adder 9. Its output code is proportional to the product of voltages at the first and second outputs of multiplexer 3. Accumulation in adder 9 takes place over several cycles of the counter 13, which forms the input voltage of the filter 15. The output code of the adder 9 is copied to block 10 and after the digital-analog conversion enters in block 22 torque sensors.

Let control is carried out according to the following algorithm:

Λί = Κΐ3'Π12; and 12 = A12 'Ny;

N1 ₀ = Ko (Αδίηφ-Ι-бсо5 <р- | -С), where Ao = const;

y, a, b, c = var.

In this case, the process of forming the code Νιο takes 3 cycles. Every beat

consists of n cycles. This number is determined by the choice of the intermediate / th digit of the counter 14, which switches the multiplexer 3. The values 5ΐηφ, cos <p are received from the corresponding sensors of block 21, the values of B, A and C are set by setpoint of block 1 of the task.

In the first cycle, during the n cycles (l periods of the output voltage of the filter 15), the value C comes to the first input of the multiplexer 3, and the voltage of the source 2, which can be made controlled, goes to the second input. For each cycle in the adder 9 accumulates the difference of unitary codes proportional to the intervals of positivity and negativity of the voltage on the integrator 6. During the first cycle these differences are summed and the sum turns out to be proportional to 1 / C or simply C. Transmitter ratio of the inverter 4 is equal to ± 1 in depending on the state of the trigger 8. In the second cycle, the first output of multiplexer 3 is the value of δϊηφ, and the second - A, so that in the adder 9 the value of С + -Ϊ-Л δίπφ is accumulated.

In the third cycle, βδοοφ is added to them. By the end of the third cycle at the input of the overflow of the counter 14, a differential occurs, overwriting the Ayu code in block 10 and resetting the adder 9. • The output impulse of element 18 can also be input to the installation inputs of counters 13 and 14, however, they can be also ringed. Counter 14 can be performed with a variable division factor, which allows you to change the algorithm, vary the integration time of the values.

Block 10 consists of a set of registers with combined information inputs and a pulse distributor, which receives pulses from the overflow output of counter 14 and distributes them to the clock inputs of the corresponding registers of block 10. The execution of the distributor 16 is determined only by the order of switching the input signals of multiplexer 3 to its outputs. It can be made in the form of a decoder, which is synthesized by known input and output sequences, taking into account the truth table of multiplexer 3.

When the voltage on the integrator 6 exceeds the set limit, a malfunction signal is generated (these can be, for example, positive and negative voltages). When the circuit 20 is made in the form of two comparators, the signals from which are fed to the element OR if the integrator voltage modulo less than the threshold, the fault signal is not generated).

1486984

Claims (1)

Claims controller containing block job pulse generator, the output of which is connected to the input of the first counter, filter, adder, comparator, characterized in that, in order to improve the control accuracy, the reference voltage source, multiplexer, integrator, zero-level detector, trigger, register block are entered into it , digital-to-analog converter, inverter-repeater, two delay elements, pulse distributor, second counter and accumulating adder, while the outputs of the reference block and the first reference voltage source are connected respectively to the first and the second information input of the multiplexer, the third information input of which is connected to the controller input, the first output of the multiplexer is connected to the first input of the adder, the output connected to the integrator input, the output of which is connected to inputs 2 of the comparator and zero level detector connected by the output to the information input £ > -trigger, the output of which is connected to the control input of the inverter-repeater and the sign input of the accumulating adder, the output of which is connected to the information input of the block of registers, The output is connected to the input of a digital-to-analog converter, the output of which is the controller output, the output of the pulse generator is connected to the clock input of the D-flip-flop and the input of the first delay element, the output of which is connected to the clock input of the accumulating adder, the installation input of which is connected to the output of the second delay element connected by the input with the clock input of the register block and the overflow output of the second counter, the clock input of which is connected to the output of the first counter and the input of the filter whose output is Connected to the second input of the adder, the third input of which is connected to the output of the inverter-repeater, connected by the information input to the second output of the multiplexer, the control input of which is connected to the output of the pulse distributor, the input of which is connected to the output of the second counter.