SU1153323A1 - Translator from binary code to binary coded decimal code - Google Patents

Abstract

BINARY CODE CONVERTER TO BINARY DECIMAL CODE, contains a pulse generator and first and second; converting sections, each of which contains a decade of a binary-decimal counter, a binary counter, a decoder zero and the element And, the first converting section contains the element OR, and the second The conversion section contains the element NOT, the output of the element AND each of the conversion sections is connected to the counting input of a binary counter, the outputs of which are connected to the inputs of the decoder zero, the first input of the element AND is connected to the output g pulse pulse, the output of the decoder zero of the second converting section is NOT connected to the second input of the element I, to the control input of the decoder zero of the first converting input and to the second input of the element And of the first converting section whose output is connected to the installation inputs of the binary counter of the second converting section and with the first input of the OR element, the second input of which is connected to the decade overflow output of the binary-decimal counter of the second conversion section, and the output of the OR element of the first conversion uyuschey section is connected to the counting input of decade of the binary coded decimal counter first transforming section vkod decoder zero first transforming section connected to the reset input of the pulse generator, the start input of which is input to the converter is started. characterized in that. in order to increase speed, a group of (N-3) transforming sections is introduced in (L), similar to the first transforming section, and an N-converting section similar to the second converting section, the second converting section contains the element I.PI, the converting sections of the group contain the element NOT, but each of the transforming secSle 00s entered contains an encoder, the outputs of which are connected to the installation inputs of the binary counter of the corresponding conversion section, the output of the element And (, N-1) conversion section with jx (ij N) converts 1h; their sections, first inputs of elements AND Vx (, ..., J) of converting sections are connected to the output of the pulse generator, the output of the decoder zero of the 14th converting section through the element connected to the second input element and transform 1c

Description

with the third input of the AND () th transforming sect and the control of the input of the zero (k-1) decoder and the transforming section, the output of the element And the second converting section are connected to the first input of the element OR the second converting section, the output which is connected to the counting input of the decade binary-decimal 53323

the second counter of the transforming section, the decade overflow of the binary-decimal counter of the k-conversion section is connected to the second input of the E-SHI element (|.: 1) -th conversion section, the output of the AND element of the conversion section is connected to the counting input decades of the binary-decimal counter of this section.

The invention relates to automation and supervisory technology and can be used in the construction of devices for processing and converting information,

A known converter of binary code into binary-decimal, containing a pulse generator, a group of binary reversible counters, a group of binary-decimal reversible counters and a group of multipliers, the outputs of which are connected to the counting inputs by a counter of groups 1 1,

The disadvantage of the well-known device lies in its relatively great complexity.

The closest in technical essence to the present invention is a binary-to-binary-to-binary converter, comprising a pulse generator, first and second converting sections, each of which contains a decade of a binary-decimal counter and a binary counter, a decoder zero, an element and NOT And out ;; which is connected to the counting inputs of the counters, and the inputs of the zero decoder are connected to the outputs of the binary counter L21,

A disadvantage of the known device is low speed,

The aim of the invention is to increase speed.

The goal is achieved by converting a binary code into a binary-decimal code containing a pulse generator and first and second converting sections, each of which contains a decade of a binary-decimal counter, a binary counter, a decoder zero and an element And the section contains an element SHIII, and the second transforming section contains an element NOT the output of the element AND each of the conversion sections is connected to a counting input of a binary counter, the outputs of which are connected to the inputs of the decoder zero, c The input element I is connected to the output of the pulse generator, the output of the decoder zero of the second conversion section is NOT connected to the second input of the element I, the control input of the decoder, the zero of the first conversion section and the second input of the element I of the first conversion section, whose QD is connected to the installation inputs of the binary counter of the second converting section and with the nepatiM input of the OR element, the second input of which is connected to the decade overflow output of the binary-decimal counter of the second converting section, the output of the OR element of the first conversion section is connected to the counting input of the decade of the binary-decimal counter of the first conversion section, the output of the decoder zero of the first conversion section is connected to the reset input of the pulse generator, the start input of which is the start input of the converter, a group of (N-3 a) conversion sections, similar to the first conversion section, and an N-conversion section, similar to the second conversion section, the second conversion section contains the element OR, the conversion Suitable groups contain -NOT section member, and each of the input converting section comprises an encoder, which outputs are connected with adjusting inputs of the binary counter corresponding to the transforming section, an output of AND (r-i (i T, ... The (N-1)) conversion section is connected to the i-th inputs of the encoder jx (j. N) conversion sections, the first inputs of the elements And the k-x (1c 3 ,.,., N) conversion sections connected to the output of the generator impulses, the output of the decoder zero of the k-th transforming secodi is NOT connected to the second input of the element AND the k-th converting section, to the third input of the element AND () -th transforming section and to the control input of the decoder zero ((.-1) - th transforming section, the output of the element AND the second transforming section is connected to the first input of the element OR the second transforming the section that is connected to the counting input of the decade of the binary-decimal counter of the second conversion section is connected to it, the output of the decade's decade of the binary-decimal conversion converter section is connected to the second input of the OR element (1s-1) -th conversion section, the output of the AND element The N-th conversion section is connected to the counting input of a decade of a binary-decimal counter of this section. The drawing shows block diagrams of the proposed converter. The converter contains N conversion sections 1 (N corresponds to the maximum n-bit input binary code). Each generator section 1 contains a decade of a binary-decimal counter 2, a binary counter 3, a decoder 4 zero element AND 5. All sections 1, except the Junior, contain the element IDN 6 all sections, except the senior, containing the element NOT 7. All The transforming sections, except for the two older ones, contain encoders 8. The converter contains a generator of 9 pulses and has a 10 start input. We denote the coefficient of recalculation of binary counters 3 through K (). : V: The device works as follows. In the initial state, in binary, 3 О t, N counters, the numbers (and, п, ..., Pr) of the binary code being converted are recorded, and the decades of the digit-decimal counters (, N) are set to zero state . In this case, the output potential of the de1b-; phrader 4 zero appears if a binary number 3 contains some non-zero number. The Start signal pulses from the output of the generator 9 through element 5 to the counting input of subtracting counting 3, and to the counting input of adding counter 2 and subtracting units from counter 3 and adding units to counter 2 (one for each pulse) to those until counter 3 is set to zero. Thus obra2. If, then there is a unit that enters through the transfer, OR 62 at the counting input counter element and in the counter 2, there remains a 2 nd chip. If (1.10, then the number 2 remains in the number of the counter. At the output of the decoder 4, a resolving potential appears, and the output of the element NOT 7 - the inhibitory. The pulse from the output of the generator 9 passes through the element 5. And subtracts the unit from the counter 3 , adding a unit to counter 2 and through the encoder 8, setting the number 1П in counter 3. The output of the decoder 4 is again: the inhibitory potential appears, and the output of the element is NOT 7 allowing the next sequence of pulses to subtract the number m from the counter 3 and adding this number to counter 2. If counter 2 overflows, the transfer unit enters through the element OR 6 to the counting input of counter 2. This sequence of actions continues cyclically until the number from counter 32 is fully transferred to counter 2. After that, AND 5 opens. the next section 1 begins the subtraction of units from counter 3 and the addition of units to counter 2 of this section, with the first impulse from the generator input 9 passing through element 5, - (t 2, N) encoder 8. (, N-2), sets the number Sl,. . ., m П KV -10 in binary meters 3; . "(I 1, N-1) of the corresponding previous sections As a result, at the output of the decoders 4; (, N-1) respectively

Claims (1)

Binary Code to Binary Decimal Code Converter, comprising a pulse generator and first and second conversion sections, each of which contains a decade of a binary decimal counter, a binary counter, a zero decoder and an AND element, the first converting section contains an OR element, and the second converting section contains the element is NOT, the output of the AND element of each of the converting sections is connected to the counting input of the binary counter, the outputs of which are connected to the inputs of the zero decoder, the first input of the And element is connected to the output of the generator and pulses, the output of the zero decoder of the second converting section through the element is NOT connected to the second input of the element And, with the control input of the zero decoder of the first converting function and with the second input of the element And of the first converting section, the output of which is connected to the setting inputs of the binary counter of the second converting section and the first input of the OR element, the second input of which is connected to the output of the decade overflow of the binary decimal counter of the second converting section, and the output of the OR element to the first converting section with it is single with the counting input of the decade of the binary decimal counter of the first converting section, the output of the zero decoder of the first converting section is connected to the reset input of the pulse generator, the start input of which is the start input of the converter, characterized in that, in order to improve performance, a group of ( N-3) converting sections, similar to the first converting section, and the N-th converting section, similar to the second converting section, and · the second converting section contains an OR element, converting group groups contain an element NOT, and each of the introduced conversion sections contains an encoder, the outputs of which are connected to the installation inputs of the binary counter of the corresponding conversion section, the output of the element And i-th G = 1, N-Г) of the converting section is connected to the i-th inputs of the encoders jx (i <j έ N) of the conversion sections, the first inputs of the elements And kx (k = 3, ..., Yu of the conversion sections are connected to the output of the pulse generator, the output of the zero decoder of the k-th conversion section through the element is NOT connected to the second input of the element And k-th will transform SU ... 1153323 of the counter of the second converting section, the output of the decade overflow of the binary-decimal counter of the k-th converting section is connected to the second input of the OR element (to ~ 1) of the converting section, the output of the AND element of the Nth converting section is connected to the counting input of the decade -decimal counter of this section. section, with the third input of the AND element (K-1) -th transforming section and with the control input of the zero decoder of the (k-1) -th transforming section, the output of the AND element of the second transforming section is connected to the first input of the OR element of the second transforming section, the output which is connected to the counting input of the decade binary-decimal