SU1462247A1

SU1462247A1 - Digital linear interpolator

Info

Publication number: SU1462247A1
Application number: SU874209281A
Authority: SU
Inventors: Анатолий Михайлович Петух; Демьян Тихонович Ободник; Александр Никифорович Романюк; Демьян Лейзерович Дрейзис
Original assignee: Винницкий политехнический институт
Priority date: 1987-03-10
Filing date: 1987-03-10
Publication date: 1989-02-28

Abstract

Изобретение относитс к автоматике и вычислительной технике и может быть использовано в устройст-. вах отображени графической информации , графопостроител х, устройствах числового программного управлени оборудованием. Целью изобретени вл етс уменьшение аппаратурных затрат и повышение надежности интерпол тора . Интерпол тор содержит ратор импульсов 1, вычитающий счетчик 2, блок пам ти 3; регистр 4, блок управлени 5, накапливающий сумматор 6, блок выходной логики.7. Введение в интерпол тор блока пам ти позволило исключить такие аппара- турно-емкие блоки как два полноразр дных регистра, два полноразр дных коммутатора, полноразр дные блоки вентилей и инверторов, а также повысить надежность интерпол тора за счет уменьшени количества св зей между его элементами и блоками. 1 з.п. ф-лы, 9 ил., 1 табл. s w JiAThe invention relates to automation and computing and can be used in devices. Wah displaying graphical information, plotters, devices, numerical control equipment. The aim of the invention is to reduce hardware costs and increase the reliability of the interpolator. The interpolator contains a pulse raptor 1, a subtracting counter 2, a memory block 3; register 4, control unit 5, accumulating adder 6, output logic block. Introduction to the interpolator of the memory block made it possible to exclude such hardware-capacious blocks as two full-sized registers, two full-sized switches, full-sized blocks of gates and inverters, as well as to increase the reliability of the interpolator by reducing the number of connections between its elements and in blocks. 1 hp f-ly, 9 ill., 1 tab. s w JiA

Description

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Здесь НСМ; - состо ние накапливающего сумматора 6 в i-м тактеi ВС - состо -ние вычитающего счегчийа 2.Here is NSM; - the state of accumulating adder 6 in the i-th cycle i BC - the state of subtractive count 2.

Блок 7 выходной логики, реализующий систему функций, заданную указанной таблицей истинности, в одном из примеров может быть реализован, как показано на фиг. 3. В этом случае он содержит элементы НЕ 43 и 50, элементы И-НЕ 44-49.The output logic block 7, which implements the system of functions defined by the specified truth table, can be implemented in one of the examples, as shown in FIG. 3. In this case, it contains the elements NOT 43 and 50, the elements AND-NOT 44-49.

Регистр 4 (фиг. 6) .вьшолнен на основе .регистра с пр мыми и инверсными входами 51.Register 4 (FIG. 6). Is executed on the basis of a register with direct and inverse inputs 51.

Пример реализаций вычитающего. счетчика 2 приведен на фиг. 7. Он содержит элемент И 52 и реверсивные счетчики 53.An example of implementations subtractive. counter 2 is shown in FIG. 7. It contains the element And 52 and reversible counters 53.

Пример реализации накапливающего сумматора 6 приведен на фиг. 8. Он содержит сумматоры 54 и регистр 55.An example implementation of the accumulating adder 6 is shown in FIG. 8. It contains adders 54 and register 55.

Пример реализации блока пам ти 3 приведен на фиг. 9. Он содержит элемент И 56 и элементы 57 пам ти. На один из входов элемента И 56 с одного из шестых входов 8 иатерпол то- ра одновременно со значением БП/2 поступает сигнал записи его в блок 3 пам ти. Блок пам ти при наличии сиг- - нала записи на входах С 2 элементов пам ти пропускает информацию сAn example implementation of the memory block 3 is shown in FIG. 9. It contains the element And 56 and the elements 57 of the memory. At one of the inputs of the element And 56, from one of the sixth inputs 8 and the mid-field, at the same time as the BP / 2 value, a signal is written to it in the memory block 3. The memory unit, in the presence of a recording signal at the inputs With 2 memory elements, passes information from

большего приращени , меньшего приращени и разности приращений нат, что позволило исключить такие с аппаратно-емкие блока, как два полно- разр дных регистра, два псшноразр д- ных коммутатора, полноразр дные блок вентилей и инверторов.higher increments, smaller increments and differences of nats increments, which made it possible to exclude such from hardware-capacious blocks as two full-registers, two switchboards, full-sized blocks of gates and inverters.

Значительное упрощение интерпо- . л тора позвол ет существенно улучшить такие технико-экономические характеристики, как габаритные размеры , потребл ема мощность, трудоемкость в изготовлении, стоимость, вес, не снижа быстродействи и точности , упростить стыковку интерпол тора с другими устройствами средств отображени и регистрации графической информации.Significant simplification of interp. This allows you to significantly improve technical and economic characteristics such as overall dimensions, power consumption, laboriousness in manufacturing, cost, weight, without reducing speed and accuracy, simplify the interpolator connection with other devices for displaying and recording graphic information.

Повышение надежности интерпол тора обеспечиваетс за счет уменьшени количества св зей между его элементами и блоками, An increase in the reliability of the interpolator is provided by reducing the number of links between its elements and blocks,

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Claims

1. Digital linear interpolator containing a pulse generator, calculus. a melting counter, accumulating a sum 30 torr, a register, an output logic block and a control block, the first input of which is connected to the output of the deducting counter, the second input - to the output of the pulse generator, the first

35 The output of the control unit is the first output of the interpolator, the second output of the control unit is connected to the counting input of the detracting counter and the first input of the output logic unit, the third output of the control unit is connected to the transfer input of the accumulating adder, the output of which is connected to the third input of the control unit different

Memory Combo skips Informat1, c- decreasing the hardware inputs of the 8 interpolator to its fb reliability enhancements

50

costs and increase the reliability of the interpolator, a memory block is inserted into it, the control and address inputs of which are connected respectively to the fourth and fifth outputs of the block

control, and the outputs - to the information outputs, and in the absence of a recording signal (reading mode), the information on the outputs of memory block 3 is determined by the value of the signal at its address input and the contents of the zero or first memory location. - to the tonal inputs of the accumulating adder, the output of which is connected to the second input of the output logic block,

p o: l to determine the evaluation function, and the gate input is connected to the sixth accumulating adder on the basis of the control unit, which is newer outside the interpolator and previously placed in the accumulating adder and memory block.

Introduction to the interpolator of the memory block allowed us to reduce the process of interchanges from the fourth to the seventh are respectively the first to the fourth inputs of the interpolator, with

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higher increments, smaller increments and differences of nats increments, which made it possible to exclude such from hardware-capacious blocks as two full-registers, two switchboards, full-sized blocks of gates and inverters.

Significant simplification of interp. This allows you to significantly improve technical and economic characteristics such as overall dimensions, power consumption, laboriousness in manufacturing, cost, weight, without reducing speed and accuracy, simplify the interpolator connection with other devices for displaying and recording graphic information.

An increase in the reliability of the interpolator is provided by reducing the number of links between its elements and blocks,

15

20

25

Invention Formula

1. A digital linear interpolator containing a pulse generator, a subtracting counter, accumulating a sum30 torus, a register, an output logic block and a control unit, the first input of which is connected to the output of the subtracting counter, the second input - to the output of the pulse generator, the first

- reduction of the device improving reliability

control, and the outputs - to the information inputs of the accumulating adder, the output of which is connected to the second input of the output logic block,

and the gate input is connected to the sixth step of the control unit, in which

inputs four through seven are respectively the first through fourth inputs of the interpolator, with

This eighth input of the control unit is connected to the fault input of the accumulating adder and the control input of the register and is the fifth input of the interpolator from the first to the fifth outputs of the register connected respectively; from the third to the seventh v inputs of the output logic block, whose outputs the first to the fourth are from the second to the fifth outputs of the interpolator, the information inputs of the detracting counter, the memory block and the register are connected to the sixth inputs of the interpolator, and the control input of the detracting counter is the seventh in interpolator house.

2. An interpolator according to claim 1, characterized in that the control unit contains the trigger circuit, four AND elements, the NAND element and the NOT element, wherein the R inputs of the first and second triggers are combined and are the eighth input of the control module The first and second inputs of the first element I are respectively the first and fifth inputs of the jmpaB-block, the output of the first element I is connected to the R inputs of the third and fourth triggers, the C input of the first trigger is connected to the S input of the second trigger, the first input the second element And is the sixth input of the block

control, the output of the first trigger is connected to the first input of the third element And, the second input of which is connected to the output of the second trigger and is the third output of the control unit, the second input of the second element And is connected to the C input of the third trigger and is the seventh input

control unit, the output of the third trigger is connected to the D-input of the fourth trigger and is the first output of the control unit; the output of the AND-NE element is connected to the C-input of the second

the trigger, the first input of the fourth element AND is the second output of the control unit, the first input of the NAND element is connected to the output of the fourth trigger, and the second input to the output of the HE element whose input is connected to the C input of the fourth trigger and the second input control unit, the D-inputs of the second and third triggers are connected to the source

Nickname of a logical unit signal, the D-input of the second trigger being the third, and the second input of the fourth element And the fourth input of the control unit, and the outputs of the second, third and fourth And elements. are the fourth, fifth and sixth outputs of the control box, respectively.

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