SU1438004A2 - Analyzer of activity of continuous signals - Google Patents

Abstract

The invention relates to automation, telemechanics and can be used in systems with adaptive discretization of continuous signals. The invention allows to increase the information content of the analyzer. When the input analog signal is received, the analyzer generates single signals: at output 13, only when the input signal increases, at output 14, when the input signal increases or decreases, at output 15, when the input signal decreases, at output 16, at times when the input signal the signal passes through points lying between the descending, increasing, and constant points. The analyzer of the activity of continuous signals contains a comparator I, a digital-to-analog converter 2, elements AND 3-6, element NOT 7, element OR 8, trigger 9, reversible counter 10, outputs 11, 12, outputs 13-16, shift register 17 and element EXCLUSIVE OR 18. 2 ill., 1 tab. sh (l

Description

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The invention relates to automation, telemechanics, can be used in systems with adaptive discretization of continuous signals and is an improvement of the invention according to the authors. St. No. 1206958.

The purpose of the invention is to increase the informativeness of the analyzer.

Fig, 1 shows the functionality of the analyzer circuit; 2 shows timing diagrams for his work.

The analyzer of the activity of continuous signals (FIG.) Contains the complexor 1, the digital-analogue converter 2, the first - the fourth element AND 3-6, the element NOT 7, the element OR 8, the trigger 9, the reversible counter 10, the first (informational) 1 and the second ( clock) 12 inputs, the first - the fourth outputs 13-16, two-bit dny shift register 17 and element 8 EXCLUSIVE HJBI.

The operation of the analyzer is based on the principle of converting analog signals to a one-bit delta code sequence with its further processing. At the first stage, the continuous analog signal X (t) is converted into a delta code sequence according to the rule

jj -

1, x; - x; s about

| oh, x; - x; about

where X (t) is a signal, previously.

recovered from the signal, and l.a L; .

At the second stage, the logical processing of the delta-code sequence signals is performed according to the rules

and,

and.

The signal and, 1 (Fig. "2c), is formed only when the two categories of the following delta-posleva symbol {) 7 coincide.

  J; -

telnosti. Moreover, if I 1, a signal is generated

50

and

a second 2 converter “Comparator 1 compares the signals X (t) and X (t). If X - X |, then the comparator 1 generates a signal L. I, which permits the passage of a pulse from the Taco input 12 through the element I 3 to the first input of the reversible counter 10. In this case, the number of pulses in the counter 10 (the state of the counter) increases by one, which causes an increase in the output voltage of converter 2 by one discreteness When Xj - X; Comparator 1 generates the signal L, О, which is fed to the input of the element NE 7. The single value of the signal at the output of the element NOT 7 permits the passage of a pulse from the clock output 14 through the element 4 and 4 to the second input of the reversing counter 10

(figg), | evidence of age- Counter 10 is reduced by

tannin but

input signal X relative-unit, which causes a decrease in

its lower value is 1 /; Oh then formed

The EC output voltage of the converter 2 is also per unit of discreteness.

50

50

five

0

45

50

signal and (figd), indicating a decrease of the input signal.

The signal and is formed at the moments of transition of the input signal X (t) through the critical points lying between the areas of increase and decrease, decrease and increase, increase and constant value, constant value and decrease, decrease and constant value, constant value and increase .

The signal and is formed only when the following one-by-one delta code sequence characters LJ 7, do not match. The table shows all possible combinations of the following three-character delta-code sequence sequences and the corresponding behavior of the input signal before and after the i-ro moment

/ time.

The analyzer works as follows.

The conversion of the input signal X (t) into a one-bit del1zTa-code sequence L j and the formation of the signal X (t), which approximates the input, occurs as follows.

An uninterrupted signal X (t) from the analyzer input is fed to the first input of comparator 1, to the second input of which a signal X (t) is fed, approximating the input, from the output of the analog converter 2 "Comparator 1 compares the signals X (t) and X ( t). If X - X |, then the comparator 1 generates a signal L. I, which permits the passage of a pulse from the clock input 12 through the element I 3 to the first input of the reversible counter 10, the number of pulses in the counter 10 (the state of the counter) increasing by one, which causes the output voltage of the converter 2 to increase When Xj - X; The comparator 1 generates the signal L, О, which is fed to the input of the element NE 7. The unit value of the signal at the output of the element NOT 7 allows the pulse to pass from the clock output 14 through the element 4 to the second input of the reversing counter 10.

The EC output voltage of the converter 2 is also per unit of discreteness.

The logical processing of the LL signals is performed as follows. The output signal of the comparator 1 is fed to the information input of the trigger 9.

Using clock pulses, inputted from input 12, trigger 9 ensures that the previous value of L is memorized, and controls the operation of AND 5 and 6. The unit state of trigger 9 ensures the passage of a single value corresponding to the case X (t) X (t ), from the output of the element And 3 through the element And 5 and at the same time the element OR 8 to the outputs 13 and 14 of the analyzer. In this case, the zero signal coming from the inverted output of the trigger 9, prohibits the passage of a single signal from the output

Element I 3 through Element I 6 on you- 20 indicate possible points on input 15 of the analyzer. If the next laziness extremum signal X (t). the time point at the output of comparator 1 also contains a single signal value, indicating an increase in signal X (t), the state of the trigger 9 does not change, and at the outputs

For synchronous and in-phase operation of the analyzer, it is necessary that the first and second inputs of the counter 10, the clock 25 inputs of the trigger 9 and the register 17 are inverse, dynamic.

13 and 14 analyzers re-form single signals. The zero state of trigger 9 permits passing

a single signal corresponding to 30 signals U; only with age X (t) “iX (t), from the output of the element I 4 through the element I 6 and at the same time the element ШШ 8 to the outputs 14 and 15 of the analyzer. At the same time, the zero signal coming from the direct output of the trigger 9 prohibits the passage of signals from the output of the element I 3 through the element 5 to the output 13 of the analyzer. The alternation of zero and single signals coming from the output of comparator 1 alternately changes the state of flip-flop 9, prohibiting the passage of single pulses from the outputs of the And 3 and 4 elements to the outputs of the analyzer.

L signal; from the direct output of the trigger 9 is fed to the information input of the shift register 17, which ensures the storage of the two previous values of the delta signals L /.,

(.

and Lj-i controls the operation of the item 18 EXCLUSIVE OR. The storage in register 17 of the two previous values of the delta signals is carried out by applying pulses to its clock input from the input 12 of the analyzer. Trigger 9 and register 17 perform the function of a three-bit shift register, at the output of trigger 9, the first and second outputs of the shift register 17 in in.

The time interval (t ,, t, v,) contains, respectively, the i-e i-l-e and i-2-e values of the delta signals. The signals from the direct output of the trigger 9 and from the output of the second bit of the register 7 are fed to the first and second inputs of the element 1 8, EXCLUSIVE OR, respectively. Single signals at the output of element 18 appear (Figure 2e) in the presence of signals of different levels at its inputs, i.e. with the fulfillment of the condition L; j 7 L ;. From the table it can be seen that it is performed only in dp times in which the signal X (t) passes through the points lying between the increasing, decreasing, and constant values of the input signal. The signals formed at the output of element 18,

indicate possible moments in terms of the extremes of the signal X (t).

For synchronous and in-phase operation of the analyzer it is necessary that the first and second inputs of counter 10, clock inputs of trigger 9 and register 17 are inverse, dynamic.

Thus, when the analyzer is fed to the input of a continuous signal X (t) at its output 13, the controller forms 55

signal X (t), single signals U are formed at output 14 (only when the signal X (t) increases or decreases, single signals U are formed at output 15 only when the signal X (t) decreases, single signals U are formed at output 16 only at times when the signal X (t) passes through points lying between

40 plots of decreasing, increasing, and constant values. There are no signals at outputs 13-16 if the input signal remains constant or changes within one quantization step.

Thus, the introduction of register 17 and element 18 EXCLUSIVE OR allows to increase the information content of the analyzer due to the temporal determination of transitions of the input signal through critical points and at the same time its delta transformation.

Claims (1)

Invention Formula Activity analyzer of continuous signals by aut. St. To 1206958, characterized in that, in order to increase the information content of the analyzer, a register and 51438004 the EXCLUSIVE OR element, information to the second input of the analyzer, the register output input and the first register input are connected to the second input of the EXCLUSIVE OR element of the switch, and the EXCLUSIVE OR element is combined, the output is connected to the first trigger output pa, the clock input of the register is connected to the lysator  O o The input signal decreases О 1 The input signal decreases and 1 starts to increase or has a constant value 1 O Input signal is constant or equal to zero I Input has a constant value or decreased and begins to increase 00 The input signal has a constant value or increased and begins to decrease O D The input signal is constant or equal to zero. 10 The input signal increased and started; . decays or remains constant Input signal increases Pig is the fourth ana. X (tl X (t) X (i) a. iillllll zUlLlLLli I d I uf inillil rLnj-LnJbft and Mill I I I I I PU2.2