SU1367157A1 - Combination a-d converter - Google Patents

Abstract

The invention relates to the field of automation and computer technology and can be used to convert the DC voltage into a digital code and enter the code into a control digital computer. The aim of the invention is to increase the noise immunity of the ADC under the influence of high-frequency periodic and impulse noise by introducing into the combined ADC, which contains a comparison unit, a trigger, a serial increment register, a reversible counter, a DAC, a pulse generator, a delay element, and an additional reversible counter. 2 pe. c (t (L

Description

with

O5

O1

The invention relates to computing and automation and can be used in digital systems for automatically controlling dynamic objects, in particular gas turbine engines, for converting signals from operating parameters sensors into a digital code.

The purpose of the invention is to increase the Balance area, and this stage

hardiness.

Figure 1 presents the block diagram of the proposed device; figure 2 is a timing diagram.

The device contains a block 1 comparing the entire stage of the follow-up equation, trigger 2, the sequence register on the read approximation bus (PTS) 3, the main signal is present, the reversible counter (PC) 4, digital -1 to the consumer reading the code of the tax converter (TSAI) 5, GEATsP.

6 pulse generator, delay element 7, additional reversible counter 8.

The device works as follows.

After arrival on the trigger bus, the trigger of the DGP 3 is reset. At the same time, at the output of the PDP, the end of the conversion establishes signal 1, which prohibits the reading of the code and simultaneously 30 and. . This signal arriving at ..

os the second inputs of reversible estimators,

But it translates both reversible counters 4 and 8 into the recording modes of parallel codes arriving at the first inputs of the counters. With the arrival of the first after the start of the clock pulse from the generator 6 of the pulses, DFD 3 begins to implement the algorithm 1 at the equilibrium equilibration. In the course of one balancing, reversible counters

35

os the second inputs of reversible estimators,

defines em - invoice direction: O - subtraction, 1 addition. The code in the counter can be changed only on the front of clock pulses, which are fed to the counting inputs of counters 4 and B

However, reversible counters operate under different conditions. The first PC 4 can only read pulses from the output. 4 and 8 do not affect the operation of the ADC. The digital overflow of the second PC 8, the arrival & bit code equal to the balancing input of the PC 4 count resolution,

is generated at the first output of the BCP 3 and transmitted through the first PC 4 to the input of the DAC 5, which produces a compensating feedback signal, compared by the comparison unit 1 with the input signal. The signals of unit 5 of block 1 are fixed on the front of clock pulses in the trigger and are rewritten in ppp 3 with a delay of the recording time in trigger 2 defined by delay element 7. After the end of bitwise equilibration (time t, in Fig. 2), a full-bit conversion code is set up at the first PEP output, and an O signal appears at the end of the PF conversion, in which the reversible counters are switched to the counting mode.

At the same time, the PCP 3 code is recorded in PC 4, and the counter begins to work from this code, and in the second PC 8, the first input is recorded into all bits of the output state of trigger 2, which can be either o or 1. time point .t, the next step starts.

It is supported by a signal O from the output of the RSH 3 until the next start pulse arrives, and the PFB itself does not affect the operation of the device in the tracking mode. During the entire stage of the follow up balancing, there is a signal on the read resolution bus, which allows the consumer to read the code

ADC.

The operation of the device at the stage of next balancing is as follows. The feedback generated from the DAC 5 is controlled by the code accumulated in the first PC 4. Depending on the sign of the difference between the input signal and the feedback signal, the output of the comparison unit 1 and then the trigger 2 generate a signal. Oh when UB i Uoe and signal G

at

30 and. . This signal arriving at ..

35

os the second inputs of reversible estimators,

defines em - invoice direction: O - subtraction, 1 addition. The code in the counters can only vary along the clock edge, which is applied to the counting inputs of counters 4 and B.

and the code 4 itself changes according to clock pulses. For the second PC 8, the account is allowed all the time, yes, therefore the input of the permission of the account is not indicated in the diagram. After completion of the pore-balancing stage, the output of flip-flop 2 is fixed to the sign of the difference between g and Uoe, having

0 place at time t ,. Assume that after the end of the work of RPP 3

u "(tO and

Step 2 is set by PC 8, the stage of the follow up balancing step 5 begins with the code value recorded from the first inputs and equal to P1 ... 1, and the counting direction in the direction of addition. Reversible counter 8 generates overflow signals

-oo (t,) and the output trigger- 1. For the second 31

according to the following logical function:

P 000 ... o subtraction;

V 1P ... 1 Addition.

Thus, at the output of the second EC 8, an overflow signal appears, and nepsbtfi PC 4 builds the code by 1. Let the condition Ug OS be fulfilled as a result of increasing the output code by 1 The state of the second PC 8 is characterized by the code 000 ... Oh, what happens when the counter overflows from above, and the counting direction determined by the output signal of trigger 2 goes in the direction of subtraction. According to this expression, the output of the second PC 8 again overlaps the overflow signal, by which the code of the first PC 4 is reduced n 1, and the second PC 8 is again set to 1 ... 1 P. Thus, when the input signal changes in the range between two adjacent quantization levels, the code of the main PC 4 with the arrival of each clock pulse changes by t1 least significant bit, and the state of the second PC 8 changes from beat to beat, taking the value 0 .. .000 and 1 ... P1. At the same time, the PC 8 each time generates an overflow signal.

When an impulse noise is applied at the input (time tj), the PC 8 code, having changed on the previous clock cycle after overflow from 1 ... 1 1 1 to 0 ... 000, with the next clock pulse, takes the value 0 ... 001, since the counting direction does not change. and therefore the overflow signal is not produced. With a constant counting direction (i.e. a constant difference of 0), the overflow signal appears only after 2 clock pulses have arrived, which is equivalent to reducing the signal tracking speed (t is the size of the additional reversing counter. For example in FIG. 2-2) those. Increase noise immunity.

Compared with the prototype, the proposed combined analog-to-digital converter, due to the introduction of the delay element, the second reversible counter and the start-up bus, has a higher noise immunity with respect to both pulsed and fast-moving continuous interference. This is due to the fact that

Q 5 about 5 about

Q

five

574

With a sharp increase in the rate of change of the input signal, which is typical of pulsed and high-frequency periodic noise, the proposed device abruptly changes the speed of tracking the input signal, as a result of which the filtering properties of the ADC increase and the stability of its operation. At the same time, the dynamic error in the frequency band of the useful signal is small, the specified conversion time at the one-bit equilibration stage, as well as the level of suppression of high-frequency and impulse noise are determined by the choice of clock values. frequency and bit size of the add-on reversible counter. For comparison, in Fig. 2, the dashed line shows the response to the impulse noise of the prototype, whence it is seen that in the prototype, all other things being equal; The conditions of disturbance from the interference is more than three times greater than the disturbance that occurs in the proposed device. In addition, in the proposed combined ADC, there are no interruptions in the work, which are spurious switches from the following mode to the counterbalance mode and back when exposed to intense pulse interference, which can occur in the prototype. This is due to the fact that the switch of the balancing method in the prototype is principally constructed so that when the error signal generated by the comparison circuit hits, the B area defined by the threshold elements will not switch to the balancing method.

Claims (1)

Invention Formula A combined analog-to-digital converter containing a comparison unit, the first input of which is an input bus, the second input is connected to the output of the digital-to-analog converter, and the output is connected to the first trigger input, the output of which is connected to the control input of the reversible counter and the information input of the serial register approximations, the information outputs of which are connected to the corresponding information inputs of the reversible counter, the counting input of which is combined with the counting input of the register successive approximations, exit 5136 The conversion end of which is the read resolution bus, and the outputs of the reversible counter are connected to the corresponding inputs of the digital-analog converter and are the output bus, a pulse generator, characterized in that, in order to increase the noise immunity, a delay element and an additional reversible signal are introduced into it. the counter, informational inputs and control input of which are connected to the trigger output, the counting input is combined with the reversing counter input 76 the counter and connected through a delay element to the output of the pulse generator, the output of which is connected to the second trigger input, the trigger input of the sequential approximation register is the trigger bus, and the write enable inputs of the reversible counter and the additional reversible counter are connected to the output of the serial approximation register the overflow output of the additional reversible counter is connected to the input of the resolution; - the reversible counter's account.