KR100286324B1 - Receive signal decrease compensation apparatus - Google Patents

Receive signal decrease compensation apparatus Download PDF

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KR100286324B1
KR100286324B1 KR1019970055063A KR19970055063A KR100286324B1 KR 100286324 B1 KR100286324 B1 KR 100286324B1 KR 1019970055063 A KR1019970055063 A KR 1019970055063A KR 19970055063 A KR19970055063 A KR 19970055063A KR 100286324 B1 KR100286324 B1 KR 100286324B1
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signal
comparator
output
flip
effective
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KR1019970055063A
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KR19990033649A (en
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권기조
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김영환
현대반도체주식회사
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M3/00—Conversion of analogue values to or from differential modulation
    • H03M3/30—Delta-sigma modulation
    • H03M3/322—Continuously compensating for, or preventing, undesired influence of physical parameters
    • H03M3/352—Continuously compensating for, or preventing, undesired influence of physical parameters of deviations from the desired transfer characteristic
    • H03M3/354—Continuously compensating for, or preventing, undesired influence of physical parameters of deviations from the desired transfer characteristic at one point, i.e. by adjusting a single reference value, e.g. bias or gain error
    • H03M3/356—Offset or drift compensation
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M3/00—Conversion of analogue values to or from differential modulation
    • H03M3/30—Delta-sigma modulation
    • H03M3/38—Calibration
    • H03M3/382—Calibration at one point of the transfer characteristic, i.e. by adjusting a single reference value, e.g. bias or gain error
    • H03M3/384—Offset correction

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  • Theoretical Computer Science (AREA)
  • Dc Digital Transmission (AREA)
  • Noise Elimination (AREA)

Abstract

PURPOSE: An apparatus for attenuating and compensating for a received signal is provided to receive selectively a signal level and a noise level by compensating for a signal attenuation without an error. CONSTITUTION: A voltage division portion(20) is used for dividing a differential input signal. A comparator(C3) is used for comparing output signals of the voltage division portion(20) and removing noises. An effective signal control portion(21) is used for receiving an output signal of the comparator(C3). The effective signal control portion(21) outputs a reception enable signal if the output signal of the comparator(C3) is data bits of 16 or more number. A data buffer portion(DB2) is used for buffering the output signal of the comparator(C3) by the reception enable signal of the effective signal control portion(21). The effective signal control portion(21) is formed with an OR gate(OR), a NOR gate(NOR), a plurality of t-flipflops(tFF1-tFF4), and a D-flipflop(DFF).

Description

수신신호의 감쇄보상장치{RECEIVE SIGNAL DECREASE COMPENSATION APPARATUS}Attenuation compensation device of received signal {RECEIVE SIGNAL DECREASE COMPENSATION APPARATUS}

본 발명은 수신신호의 감쇄보상장치에 관한 것으로, 특히 매체의 길이에 따른 신호의 감쇄와 매체의 노후화에 따른 신호의 감쇄를 에러 없이 보상하여 신호레벨과 노이즈레벨을 구별하여 수신하는데 적당하도록 한 수신신호의 감쇄보상장치에 관한 것이다.The present invention relates to an attenuation compensation device for a received signal, and more particularly, to compensate for attenuation of a signal according to a length of a medium and attenuation of a signal due to an age of a medium without error, and receiving a signal suitable for distinguishing and receiving a signal level and a noise level. Attenuation compensation device of the signal.

도1은 종래 수신신호의 감쇄보상장치의 구성을 보인 회로도로서, 이에 도시된 바와같이 전원전압(VDD)과 접지(GND)사이에서 각기 직렬 접속된 저항(R11~R14)과 직렬 접속된 저항(R15),(R16)이 병렬로 접속되고, 상기 저항(R11)과 저항(R12)의 접속점에 차동입력신호(RD-)를 인가하고, 상기 저항(R15)과 저항(R16)의 접속점에 차동입력신호(RD+)를 인가하며 그 접속점을 비교기(C1),(C2)의 일측 입력단에 접속하고, 상기 비교기(C1)의 타측 입력단에 저항(R12),(R13)의 접속점을 접속하며, 상기 비교기(C2)의 타측 입력단에 저항(R13),(R14)의 접속점을 접속하고, 상기 비교기(C2)의 출력신호를 인에이블단자에 인가받고 상기 비교기(C1)의 출력신호를 입력단에 인가받는 데이터버퍼(DB1)로 구성되며, 이와 같이 구성된 종래 장치의 동작을 설명한다.FIG. 1 is a circuit diagram showing the structure of a conventional attenuation compensation device for a received signal. As shown in FIG. 1, a resistor connected in series with a resistor R11 to R14 connected in series between a power supply voltage VDD and a ground GND, R15 and R16 are connected in parallel, and a differential input signal RD- is applied to the connection point of the resistor R11 and the resistor R12, and differentially connected to the connection point of the resistor R15 and the resistor R16. The input signal RD + is applied and its connection point is connected to one input terminal of the comparators C1 and C2, and the connection point of the resistors R12 and R13 is connected to the other input terminal of the comparator C1. The connection point of the resistors R13 and R14 is connected to the other input terminal of the comparator C2, and the output signal of the comparator C2 is applied to the enable terminal and the output signal of the comparator C1 is applied to the input terminal. The operation of the conventional device configured as the data buffer DB1 and configured as described above will be described.

먼저, 비교기(C1)는 차동입력신호(RD+)(RD-)의 신호차가 저항(R11~R14)에 의해 분압되는 오프셋전압(V0=(R12/(R11+R12+R13+R14))

Figure pat00001
VDD) 이상인 입력데이터 신호는 상기 비교기(C1)를 통해 출력되고, 상기 오프셋전압(V0)보다 낮은 입력데이터 신호는 억제되어 입력되지 않는다.First, the comparator C1 has an offset voltage (V0 = (R12 / (R11 + R12 + R13 + R14)) in which the signal difference between the differential input signals RD + and RD- is divided by the resistors R11 to R14.
Figure pat00001
The input data signal above VDD) is output through the comparator C1, and the input data signal lower than the offset voltage V0 is suppressed and is not input.

또한, 수신신호 감지신호가 차동입력신호(RD+)(RD-)의 차 보다 크면 비교기(C2)는 인에이블신호를 출력하여 그 인에이블신호에 의해 수신데이터버퍼(DB1)를 인에이블시켜 유효수신데이터를 받아들이고, 반대로 상기 수신신호 감지신호가 차동입력신호(RD+)(RD-)의 차보다 작으면 노이즈 억제 수신 데이터가 있어도 데이터를 받아들이지 않는다.If the received signal detection signal is larger than the difference between the differential input signals RD + and RD-, the comparator C2 outputs an enable signal and enables the received data buffer DB1 by the enable signal to enable effective reception. On the contrary, if the received signal detection signal is smaller than the difference between the differential input signals RD + and RD−, the data is not received even if there is noise suppression received data.

그러나, 상기와 같이 동작하는 종래 장치는 매체에서 노이즈를 차단하기 위한 억제신호레벨과 수신신호 감지레벨이 고정되어 있어 매체의 길이에 따른 신호의 감쇄와 매체의 노후화에 따른 신호의 감쇄가 커지면 수신이 차단되는 문제점이 있었다.However, in the conventional apparatus operating as described above, the suppression signal level and the reception signal detection level for blocking noise in the medium are fixed, so that when the attenuation of the signal according to the length of the medium and the attenuation of the signal due to the aging of the medium become large, the reception is stopped. There was a problem blocking.

따라서, 상기와 같은 문제점을 감안하여 창안한 본 발명은 매체의 길이에 따른 신호의 감쇄와 매체의 노후화에 따른 신호의 감쇄를 에러없이 보상하여 신호레벨과 노이즈 레벨을 구별하여 수신할 수 있도록 한 수신신호 감쇄보상장치를 제공함에 그 목적이 있다.Accordingly, the present invention has been made in view of the above problems, and the present invention can compensate for the attenuation of the signal according to the length of the medium and the attenuation of the signal due to the aging of the medium without error, so that the signal level and the noise level can be distinguished and received. It is an object of the present invention to provide a signal attenuation compensation device.

도 1은 종래 수신신호의 감쇄보상장치의 구성을 보인 회로도.1 is a circuit diagram showing a configuration of an attenuation compensation device of a conventional received signal.

도 2는 본 발명 수신신호의 감쇄보상장치의 구성을 보인 회로도.Figure 2 is a circuit diagram showing the configuration of the attenuation compensation device of the received signal of the present invention.

도 3은 도 2에 있어서, 각 부분의 타이밍도.3 is a timing diagram of each part in FIG. 2;

*****도면의 주요부분에 대한 부호의 설명********** Description of the symbols for the main parts of the drawings *****

20:분압부 21:유효신호제어부20: voltage divider 21: effective signal controller

DB2:데이터버퍼 tFF1~tFF4:티플립플롭DB2: Data buffer tFF1 to tFF4: Flip-flop

DFF:디플립플롭 C3:비교기DFF: Deflip Flop C3: Comparator

상기와 같은 목적을 달성하기 위한 본 발명은 차동신호를 입력받아 이를 분압하는 분압부와; 상기 분압부의 제1,제2 출력신호를 입력받아 그 두신호의 차와 오프셋 전압과의 크기를 비교하는 비교기와; 상기 비교기의 출력신호를 입력받아 이 출력신호가 16개이상의 데이터비트이면 수신 인에이블신호를 출력하는 유효신호제어부와; 상기 유효신호제어부의 수신 인에이블신호에 의해 상기 비교기의 출력신호를 버퍼링하는 데이터버퍼부로 구성한 것을 특징으로 한다.The present invention for achieving the above object is a voltage divider for receiving a differential signal and divides it; A comparator that receives the first and second output signals of the voltage divider and compares the difference between the two signals and an offset voltage; An effective signal controller for receiving an output signal of the comparator and outputting a receive enable signal if the output signal is 16 or more data bits; And a data buffer unit for buffering the output signal of the comparator according to the reception enable signal of the effective signal controller.

이하, 본 발명에 의한 수신신호 보상장치에 대한 작용 및 효과를 첨부한 도면을 참조하여 상세히 설명한다.Hereinafter, with reference to the accompanying drawings, the operation and effects of the reception signal compensation apparatus according to the present invention will be described in detail.

도2는 본 발명 수신신호 보상장치의 구성을 보인 일실시예의 회로도로서, 이에 도시한 바와같이 차동입력신호(RD-),(RD+)를 입력받아 이를 분압하는 분압부(20)와; 상기 분압부(20)의 출력신호를 입력받아 이를 비교하여 미소 노이즈를 제거하는 비교기(C3)와; 상기 비교기(C3)의 출력신호를 입력받아 이 출력신호가 16개이상의 데이터 비트이면 수신 인에이블신호를 출력하는 유효신호제어부(21)와; 상기 유효제어부(21)의 수신 인에이블신호에 의해 상기 비교기(C3)의 출력신호(VRD)를 버퍼링하는 데이터버퍼부(DB2)로 구성한다.Figure 2 is a circuit diagram of an embodiment showing the configuration of the received signal compensation device of the present invention, as shown therein, a voltage divider 20 for receiving the differential input signal (RD-), (RD +) and divides it; A comparator (C3) for receiving the output signal of the voltage dividing unit 20 and comparing the same to remove the minute noise; An effective signal controller 21 for receiving the output signal of the comparator C3 and outputting a receive enable signal if the output signal is 16 or more data bits; The data buffer unit DB2 buffers the output signal VRD of the comparator C3 according to the reception enable signal of the effective control unit 21.

상기 유효신호제어부(21)는 일측에 리셋신호(RESET)를 입력받고 타측에 도3의 (c)와 같은 링크신호(LNKC)를 입력받아 이를 오아 연산하는 오아게이트(OR)와; 상기 오아게이트(OR)의 연산신호를 입력받고 타측에 수신 인에이블신호를 입력받아 이를 노아 연산하는 노아게이트(NOR)와; 상기 노아게이트(NOR)의 연산신호를 클리어단자에 인가받고 비교기(C3)의 출력신호를 클럭단자(CP)에 인가받아 이를 티플립플롭하는 티플립플롭(tFF1~tFF4)과; 상기 티플립플롭(tFF1~tFF4)의 출력신호를 디입력단자에 인가받고 상기 오아게이트(OR)의 연산신호를 인버터(IN)를 통해 클리어단자에 인가받아 이를 디플립플롭하여 수신 인에이블신호를 출력하는 디플립플롭(DFF)으로 구성되며, 이때 상기 티플립플롭(tFF2~tFF4)은 전 티플립플롭(tFF1~tFF3)의 출력신호를 클록단자(CP)에 인가받도록 구성하며, 이와같이 구성한 본 발명의 일실시예의 동작을 도3의 타이밍도를 참조하여 설명한다.The effective signal controller 21 includes an oragate (OR) that receives a reset signal (RESET) on one side and receives a link signal (LNKC) as shown in FIG. A NOR gate (NOR) for receiving the operation signal of the OR gate and receiving a receive enable signal on the other side to perform a NOR operation on the reception signal; A tip flip-flop (tFF1 to tFF4) for receiving the operation signal of the NOR gate (NOR) to the clear terminal and receiving the output signal of the comparator (C3) to the clock terminal (CP); The output signal of the flip-flop tFF1 to tFF4 is applied to the de-input terminal, the operation signal of the OR gate OR is applied to the clear terminal through the inverter IN, and then flip-floped to receive the receive enable signal. The flip-flop (DFF) for outputting, wherein the flip-flop (tFF2 ~ tFF4) is configured to receive the output signal of all the flip-flop (tFF1 ~ tFF3) to the clock terminal (CP), this configuration The operation of one embodiment of the invention will be described with reference to the timing diagram of FIG.

먼저, 분압부(20)는 차동입력신호(RD-),(RD+)를 입력받아 이를 오프셋저항(R22)에 의해 분압하여 출력함과 아울러 저항(R24),(R25)에 의해 분압된 신호를 출력한다.First, the voltage dividing unit 20 receives the differential input signals RD- and RD +, divides them by the offset resistor R22, and outputs them, and also divides the signals divided by the resistors R24 and R25. Output

이때, 상기 오프셋 저항(R22)에 의해 발생하는 신호(V0)의 크기를 식으로 나타내면 아래와 같다.In this case, the magnitude of the signal V0 generated by the offset resistor R22 is expressed as follows.

V0=(R22/(R21+R22+R23))

Figure pat00002
VDDV0 = (R22 / (R21 + R22 + R23))
Figure pat00002
VDD

이때, 비교기(C3)는 상기 분압부(20)의 오프셋저항(R22)에 의해 분배된 전압(V0)의 차만큼 수신신호에서 미소 노이즈를 억제하여 데이터를 수신하는데, 만약 차동입력신호(RD-),(RD+)의 차가 상기 오프셋저항(R22)에 의해 분압된 신호(V0)보다 적으면 미소 노이즈 억제 수신데이터로 되어 비교기(C3)의 출력은 변하지 않는다At this time, the comparator C3 receives the data by suppressing the minute noise from the received signal by the difference of the voltage V0 divided by the offset resistor R22 of the voltage divider 20. If the differential input signal RD− If the difference between RD + and RD + is smaller than the signal V0 divided by the offset resistor R22, the noise is suppressed and the output of the comparator C3 is not changed.

상기와 달리, 차동입력신호(RD-),(RD+)의 차가 상기 오프셋저항(R22)에 의해 분압된 신호(V0)보다 크면 수신데이터는 비교기(C3)에서 로직데이터로 변환되어 데이터버퍼(DB2) 및 유효신호제어부(21)의 티플립플롭(tFF1)의 클럭단자(CP)에 입력된다.Unlike the above, when the difference between the differential input signals RD- and RD + is larger than the signal V0 divided by the offset resistor R22, the received data is converted into logic data in the comparator C3 and the data buffer DB2. And the clock terminal CP of the flip-flop tFF1 of the effective signal controller 21.

여기서, 상기 유효신호제어부(21)의 티플립플롭(tFF1~tFF4)은 상기 비교기(C3)에서 출력된 수신 데이터의 변환이 감지되면 카운팅을 시작하여 연속된 데이터의 변환이 16회 이상 계속될때 디플립플롭(DFF)의 클럭단자(CP)을 인에이블하여 이 디플립플롭(DFF)의 출력을 도3의 (e)와 같이 고전위신호로 출력하며, 이에따라 데이터버퍼(DB2)는 상기 디플립플롭(DFF)의 도3의 (e)와 같은 고전위신호에 의해 유효수신데이터를 생성한다.Here, the tip flip-flops tFF1 to tFF4 of the valid signal control unit 21 start counting when the conversion of the received data output from the comparator C3 is detected and the conversion of the continuous data continues 16 times or more. By enabling the clock terminal CP of the flip-flop DFF, the output of the de-flop flop DFF is output as a high potential signal as shown in (e) of FIG. 3, and accordingly, the data buffer DB2 receives the deflip. Effective reception data is generated by the high potential signal as shown in Fig. 3E of the flop DFF.

즉, 도3의 (a)와 같은 리셋신호(RESET)와 도3의 (c)와 같은 링크신호(LNKC)는 상기 유효신호제어부(21)를 초기화하여 데이퍼버퍼(DB2)의 수신 인에이블신호를 초기화하고, 16회 이상의 유효데이터가 입력되었을때 데이터버퍼(DB2)를 인에이블하여 유효수신데이터가 생성된다.That is, the reset signal RESET as shown in FIG. 3A and the link signal LNKC as shown in FIG. 3C initialize the valid signal controller 21 to enable reception of the data buffer DB2. When the signal is initialized and valid data is input 16 times or more, the data buffer DB2 is enabled to generate valid received data.

여기서, 상기 유효수신데이터는 제어기(미도시)에 의해 수신 데이터의 처리 및 제어가 이루어지며, 또한 도3의 (f)와 같이 유효수신데이터가 계속되는 구간은 도3의 (b)와 같은 캐리어 감지신호가 고전위로 생성되어 수신 데이터 구간을 표시한다.In this case, the valid reception data is processed and controlled by a controller (not shown), and a section in which valid reception data continues as shown in FIG. 3 (f) detects a carrier as shown in FIG. The signal is generated at high potential to indicate the received data interval.

이상에서 상세히 설명한 바와같이 본 발명은 차동 입력 수신신호의 작은 차이도 감지할 수 있어 신호의 감쇄가 큰 매체에서도 유효 수신 데이터의 신뢰도가 향상됨과 아울러 비교기의 수를 절감하고 아나로그 부분을 디지털로 변환하여 구성하므로 제작이 용이하고 제품의 신뢰성을 향상시킬 수 있는 효과가 있다.As described in detail above, the present invention can detect a small difference in the differential input received signal, thereby improving the reliability of valid received data even in a medium having a large signal attenuation, reducing the number of comparators and converting analog parts to digital. Since the configuration is easy to manufacture and has the effect of improving the reliability of the product.

Claims (3)

차동신호를 입력받아 이를 분압하는 분압부와; 상기 분압부의 제1,제2 출력신호를 입력받아 그 두신호의 차와 오프셋 전압과의 크기를 비교하는 비교기와; 상기 비교기의 출력신호를 입력받아 이 출력신호가 16개이상의 데이터비트이면 수신 인에이블신호를 출력하는 유효신호제어부와; 상기 유효신호제어부의 수신 인에이블신호에 의해 상기 비교기의 출력신호를 버퍼링하는 데이터버퍼부로 구성한 것을 특징으로 하는 수신신호의 감쇄보상장치.A voltage dividing unit configured to receive the differential signal and divide the same; A comparator that receives the first and second output signals of the voltage divider and compares the difference between the two signals and an offset voltage; An effective signal controller for receiving an output signal of the comparator and outputting a receive enable signal if the output signal is 16 or more data bits; And a data buffer unit for buffering the output signal of the comparator according to the receive enable signal of the effective signal control unit. 제1 항에 있어서, 유효신호제어부는 리셋신호와 링크신호를 오아 연산하는 오아게이트와; 상기 오아게이트의 연산신호와 피이드백된 수신 인에이블신호를 노아 연산하는 노아게이트와; 상기 노아게이트의 연산신호를 클리어단자에 인가받고 비교기의 출력신호를 클럭단자에 인가받아 이를 티플립플롭하는 제1~제4 티플립플롭과; 상기 제4 티플립플롭의 출력신호를 디입력단자에 인가받고 상기 오아게이트의 연산신호를 인버터를 통해 클리어단자에 인가받아 이를 디플립플롭하여 그에 따른 수신 인에이블신호를 출력하는 디플립플롭으로 구성한 것을 특징으로 하는 수신신호의 감쇄보상장치.2. The apparatus of claim 1, wherein the valid signal control unit comprises: an orifice for ORing a reset signal and a link signal; A noa gate for performing a NOR operation on the operation signal of the ora gate and the feedback enable enable signal; First to fourth flip-flops that receive the operational signal of the NOA gate to the clear terminal and to flip-flop the output signal of the comparator to the clock terminal; The output signal of the fourth flip-flop is applied to the de-input terminal, and the operational signal of the oragate is applied to the clear terminal through an inverter to de-flip the flip-flop to output the received enable signal accordingly. Attenuation compensation device of the received signal, characterized in that. 제 1 항에 있어서, 유효수신제어부는 정해진 소정 비트구간 이상 수신데이터가 반복될 때 데이터 수신 인에이블신호를 발생하는 것을 특징으로 하는 수신신호의 감쇄보상장치.2. The apparatus of claim 1, wherein the effective reception controller generates a data reception enable signal when the received data is repeated over a predetermined predetermined bit section.
KR1019970055063A 1997-10-25 1997-10-25 Receive signal decrease compensation apparatus KR100286324B1 (en)

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