SU1430970A1 - Device for adding pulse durations - Google Patents

Abstract

The invention relates to automation and computing and can be used in digital computers. The aim of the invention is to increase the speed and the expansion of the field of application due to the parallel summation or subtraction of the pulse durations. The device contains K summation blocks, each of which contains p bistable elements, a group of elements OR, a group of elements AND, for pulse shapers, prohibition elements, an addition bus, a subtraction, a transfer, a loan. In addition, the device contains a pulse duration shaping unit, pulse inputs, an addition and subtraction mode control input, and the first summation unit additionally contains groups of AND elements, the AND-NES element, and two NOT elements. The information in the device is represented in a single-normal code. Addition and subtraction of pulse durations can be done both in parallel and in series. 1 hp f-ly, 2 ill. (L

Description

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The invention relates to automation and computing and can be used in digital computers.

The purpose of the invention is to increase the speed and expansion of the application area of the device due to the parallel summation or subtraction of the pulse number.

FIG. I shows a block diagram of the proposed device; Fig. 2 is a block diagram of the formation of pulse durations.

The device contains K blocks 1-1-suming, each of which contains n bistable elements 2, with inputs 3 and 4 set to 1 and O, respectively, the first group of elements OR 5, the second group of elements OR 6, the first group and 7, the second group of elements, and 8, two formers of 9 pulses, the first 0 and second of the prohibition elements, folding distance 12, subtraction bus 13, transfer bus 14, loan bus 15, pulse shaping unit 16, the first 17 and second 18 pulse inputs and an input 19 control of the modes of addition and subtraction.

In the first block C, the summation additionally includes the third group of elements AND 20, the fourth group of elements AND 21-24, the element IS-NOT 25 and the two elements NOT 26 and 27. The block 16 of forging pulse widths contains the first to third outputs 28- 30, the signal inputs 31 and 32, the control input 33, the fourth output 34, the elements HE 35 and 36, the elements AND 37-40 and the element OR 41 and 42.

The device works as follows.

Each block is 1, -1. contains an even number of bistable elements, i.e. n 2 1 (1 1, K).

The information in the device is represented in a single normal code.

Addition and subtraction of pulse durations can be done both in parallel and in series.

To successively add pulse durations, logical O is fed to input 19 of the device, and the first 17 or second 18 inputs of the device feed the first pulse to the first 31 or second 32 inputs of the pulse width forming unit 16 and passing through it

the output 34 coming from there to the add-on bus 12, and the signal from the output of the prohibition element 10 through the element OR 5 is fed to the input 3 of the installation in the unit state of the bistable element 2, causing it to be set to the logical state 1, which appears on the unit output, giving permission to switch the next bistable element, etc. The last bistable element 2, when set to the state of logical 1, gives permission for the formation and myca of transfer from the output of the second generator of 9 pulses, with the same impulse all bistable elements except the first one in the first group are set to the state of logical O by input 4 setting to zero through the elements OR 6, while the duration (, 4c of the pulse is determined by the maximum switching time of the bistable elements. The first bistable element 2 is not set to the state About Skogen,

only when the input I pulse continues to be present

. on one of the two inputs 17 or 18 of the device and after the installation time is over to the state of logical 1 of the last bistable element 2 of the first group, after time Ser, max. the first bistable element 2 of the next group will enter the state of logical I, and the first bistable element 2 the first group will remain in a logical 1 state only if

t 7 p

gr.sr

where t is the pulse duration at the input 17 or 18 of the device;

.cf is the average response time of one bistable element.

The first bistable element 2. of the first group remains in the state of logical 1, since from the output 30 of block 16 to the input of the first element NOT 26 a signal of logical 1 is received, which is converted to logical O and fed to the first input of the third element I 23, the output of which there will also be a logical O coming through the second element OR 6 to the zero input of the first bistable element 2,

314

which, in turn, does not enter the state of logical O. For successive subtraction of the pulse durations, a reduced pulse is inserted into the device. The process of recording a decrementing pulse is similar to the described sequential add mode.

When information arrives at the subtraction bus 13, the signal from the output of the prohibition element 1 1 enters the elements And 8 and appears at the outputs of those elements 8, the second inputs of which from the zero outputs of the bistable elements receive a logical 1 signal, i.e. these bistable elements are in a state of logical O

Suppose that in a decade in a state of logical 1 there are i bistable elements, therefore, in a state of logical O there are n – i bistable elements 2 -, - 2. From the zero output (bistable element 2;., Through the element And 8, the signal of logical 1 is fed through the element OR 6 to the input 4 of the setting in the zero state of the bistable element 2 |, causing its installation to the state O, i.e. at its zero output, logic appears: 1, giving permission to switch the next bistable element 2 i, etc. At the same time, a logical output O appears at the unit output of the i-ro bistable element 2- and so on.

The first bistable element 2, when set to the logical O state, allows the formation of a transfer pulse from the output of the first pulse shaper circuit, with the same pulse all bistable elements are set to the logical 1 state by acting on the inputs 3 of the unit in one state through the elements OR 6, wherein the pulse duration is determined by the maximum switching time.

The last bistable element 2 p is set to the state of logical 1 only if a single signal is not supplied from the subtraction bus 13 at this moment. At the output of the second element NOT 27 there is a signal of logical 1, which through the fourth element And 24 and the element OR 5 enters the single input 3 of the last bistable element 2.

70

Through the loan bus 15, the highest bistable element of the second group, which is in the logical 1 state, passes to the zero state.

For the simultaneous addition of two pulse durations, logical O is fed to the input 19 of the device, and summable pulses are fed to the first 17 and second 18 inputs. All of them are fed to the inputs 31-33 of block 16. As a result, the output 34 of block 16 will have a pulse with a duration equal to the longest duration of one of the summed pulses.

Thus, the device can sum the pulse durations coinciding along the leading edges, and the summation occurs in a time equal to the pulse duration with a longer duration.

If summable pulses are simultaneously applied to the first two inputs 17 and 18 of the device, the first two bistable elements 2 and 2 of the first group are simultaneously set to one due to the fact that logical outputs are supplied from the two outputs 28 and 29 of the block 16 1, and from the output of the element 21, through the elements OR 5, a single signal is fed to the single inputs 3 of the first two bistable elements 2, and 2, causing them to be set to the logical 1 state, which appears on the single outputs, giving the permission to switch the following x two bistable elements 2 and 2. A single signal from an output of an AND 7 element, the first input of which is connected to a single output of a bistable element 2, goes to the third input of a second element AND 20, a signal from an output of which through elements OR 5 enters to a single input 3 of bistable elements 2 and 2, thereby causing them to be set to logical 1, and so on.

The last bistable element 2, when set to the logical 1 state, gives permission for the formation of a transfer pulse from the output of the second driver 9 pulses. By the same impulse, all bistable elements are set to the logical state O by acting on the inputs 4 of the installation to the zero state through the elements OR 6, while the pulse duration is determined by the maximum

switching time of bistable elements.

If the first two inputs 17 and 18 of the device continue to have two pulses, then the bistable element of the next group passes into the logical 1 state, and in the first group remain in the same unit at the output of block 16 there will be two pulses with durations equal to the duration from the leading edge of the decreasing pulse to the leading edge of the subtracted pulse and from the falling edge of the subtracted pulse to the falling front of the decreasing pulse, i.e. block 16

In the first state, the first bistable o cuts the pulse power (two elements 2 and 2, since from the outputs of the pulses) obtained as a result of 28-30 block 16 to the inputs of the element 25 and the element HE 26 are fed

subtraction. The resulting impulse goes to the addition bus and the further recording process is similar.

logical signals 1. At the exits

He elements 26 and I-He 25 appear as a process of sequential summation O arriving through AND elements 23 and 22 and OR elements 6 to the zero inputs 4 of the first two bits of elements 2 and 2, thereby not causing their switching. In the future, the process of addition occurs in a similar way.

From the point in time when a pulse with a shorter duration ends, the addition occurs in the same way as the addition with successive summation, until the end of the pulse with a longer duration.

. In order to parallel two pulse durations, the input 19 of the device sends a logical 1 signal, and the first 17 and second 18 inputs of the device, respectively, are given a pulse-down and a subtracted pulse, and the moments of the presence of both pulses must meet the conditions

thirty

neither described above.

Thus, the device can sum and subtract pulse durations in series and in parallel.

The pulse addition and subtraction unit 16 operates as follows.

In the modes of addition to po- 25 a logical O is given, and logical 1, input through elements 38 and 39 (due to the presence of the output at the element NO logical O) at the inputs of the element OR 41 and outputs 28 and 29 is fed to the inputs 31 and 32. the output of the element OR 41 a single signal goes to the output 30 and through the element OR 42 to the output 34 of block 16. If one pulse is present at one of the two inputs of block 16, then the output of the element OR 41 will also have a logical I.

35

 one

about.

where t is the pulse presence time

deductible

t is the time of the presence of a pulse reduced.

Thus, the presence of the subtracted pulse does not loosen

In parallel mode, logical 1 is fed to input 32 of block 16, as well as input of element 37. From output of element 35, the second outputs of first and second elements 38 and 39 are logically O. Therefore, at the output of element OR 41 and 1 input 28 and 29 there is a logical O If a pulse is present at the output 30, and a pulse is not present at the input 31, then the first input of the I 40 element from the first output 30 of the block

the time frame of presence is decremented and to the second input from the output of the second

th pulse.

The block 16 at the output 34 forms an im- pulse, the duration of which corresponds to the tit-presence of the element NOT 36 enters the logical 1. From the output of the element AND 40 through the element 37 and the second element OR 42 a single signal enters the time t j

VIA only diminished impulse. Time-55 is run 34 of block 16. If the pulses of the presence of two pulses simultaneously are ignored. If the pulses on the leading edges do not match.

cuts the power of the pulse (two pulses) resulting from

subtraction. The resulting impulse goes to the addition bus and the further recording process is similar.

0

neither described above.

Thus, the device can sum and subtract pulse durations in series and in parallel.

The pulse addition and subtraction unit 16 operates as follows.

In the modes of addition to po- 5 is given a logical O, and logical inputs 1, which flow through AND 38 and 39 elements (due to the presence of NO logical O elements at the output of the element), to the inputs of the OR 41 element and to outputs 28 and 29 are given to the inputs 31 and 32. the output of the element OR 41 a single signal goes to the output 30 and through the element OR 42 to the output 34 of block 16. If one pulse is present at one of the two inputs of block 16, then the output of the element OR 41 will also have a logical I.

In parallel mode, logical 1 is fed to input 32 of block 16, as well as input of element AND 37. Logic O is output from HE 35 to second outputs of first and second elements 38 and 39 and logical O is received. Therefore, OR 41 and to inputs 28 and 29 there is a logical O. If a pulse is present at the output 30, and a pulse is not present at the input 31, then to the first input of the element 40 from the first output 30 of block 16

five

0

element 36 enters logical 1. From the output of the element 40 and through the element 37 and the second element OR 42, a single signal arrives at the first two inputs 31 and 32 of block 16, then the output of the element 40 will have a logical

 o, which also arrives at 1-stroke 34 of block 16.

Claims (2)

1. A device for summing pulse durations, containing K summation blocks, each of which contains p bistable elements, two prohibition elements, two pulse shapers, two groups according to para. And elements and two groups according to n elements OR, and in each jth (. K) summation block the single output i-ro (i 1, n) of the bistable element is connected to the first input of the i-ro element AND of the first group connected output with the first input (i + l) -ro of the element OR of the first group, the output of which is connected to the input of the installation in 1 (i + l) -ro of a bistable element connected by zero output with the first input of (i + l) -ro of the element AND the second the group connected by the output to the first input of the i-ro of the element OR of the second group, the output of which is connected to the input of the installation in the О i-ro element, and the output of the first element OR of the first group is connected to the input of the first 1 bistable element connected to the first input of the first element AND of the second group connected to the input of the first pulse shaper, the second inputs of the AND elements of the first group and the first input the first element OR of the first group is connected to the output of the first interdiction element connected by the first input to the second inputs from the third to the fifth elements OR of the second group and the output of the second impulse generator owls connected by the input to the output of the nth element AND of the first group, and the second inputs of the elements AND of the second group and the second input of the nth element OR of the second group are connected to the output of the second prohibition element connected by the first input to the output of the first imposer and second inputs the first by (p-1) -th element OR of the first group, and in each j-M summation block, with the exception of the first block, the output of the first pulse generator is connected to the second input of the n-th element OR of the first group, the output of the second pulse former is Inonu WTO thirty , , | 0 15 20 25 35 40 45 50 five the primary inputs of the first and second elements OR of the second group, the second inputs of the first and second elements of the prohibition of the j-ro summation block are connected to the outputs of the second and first pulse shapers (J-1) -th summation block, respectively, and the second inputs of the first and second elements the prohibition of the first summation block is connected to the addition and subtraction tires of the device, respectively, characterized in that, in order to increase speed and expand the scope of application by parallel summing or subtraction of the durations pulses, a pulse duration shaping unit has been entered into it, and the first summation block. additionally contains the third group of (p-2) / 2 elements AND, the fourth group of four elements AND, two elements NOT and the element AND-NOT, while the block forming pulse durations is connected by the first and second signal inputs to the first and second pulse inputs of the device the control input to the control input of the addition and subtraction modes of the device, the first and second outputs respectively to the first and second inputs of the AND elements of the third group, the first and second inputs of the first element of the fourth group, and the first and second inputs element AND-NOT, the third output to the input of the first element is NOT, and the fourth output to the second input of the first element is the prohibition of the first summation unit, and in the first summation unit the output of the first AND element of the fourth group is connected to the third inputs of the first and second elements OR The first group, the second element of the fourth group is connected to the output of the second input of the second element OR of the second group, the first input to the output of the NAND element, and the second input to the output of the second pulse shaper and the first input of the third element And the fourth group connected by the second input with the output of the first element is NOT, and the output is with the second input of the first element OR of the second group, while the fourth element of the fourth group is connected to the second input of the n-th element OR of the first group, the first input to the output the first pulse former, and the second input - to the output the second element NOT connected with the input to the subtraction bus of the device, with each 1st l 61 (n-2) "-2j element AND of the third group connected by a third input to the output (2 -1) -th element AND of the first group, and output - to the third input of the 2 (1 + 1) -th element OR of the first group. , 2. The device according to claim I, of which is, in that the pulse width forming unit contains four elements AND, two ICA elements and two NOT elements, the first element is NOT connected by an input to the control input of the pulse width forming unit and the first input of the first element is And, and the output is to the first inputs of the second and third elements And, with the second element And connected by the second input to the first signal input of the pulse duration shaping unit and the first input of the fourth element And, and it is. house - with the first output of the pulse duration shaping unit and the first input of the first OR element connected by the second input to the output of the third element AND and the second output of the pulse duration forming unit, and the output to the first input of the second OR element connected with the second input of the first AND output , the second input of which is connected to the output of the fourth element And connected to the second input with the output of the second element NOT connected to the second input of the third element And the second signal input of the block forming the pulse durations, and the outputs of the first and second elements OR are connected respectively to the third and fourth outputs of the block forming the durations of the pulses. .d Fi, g. one