SU1416979A1 - Device for determining the volume of sampling of monitoring parameters - Google Patents

Abstract

The invention relates to computing and can be used in determining the operational and technical characteristics of complex technical systems, for example, to determine the number of parameters for monitoring the technical state of such systems. The purpose of the invention is to expand the functionality of the device by determining the minimum amount of control parameters of a technical system with a total methodical probability equal to one. The essence of the invention consists in the hardware solution of the problem of determining the minimum amount of control parameters by simulating a oriented graph of the structure of a technical object and analyzing the reachability matrices of the vertices of the graph. 5 il. with (L

Description

O5 UD O

The invention relates to computing and can be used in determining the operational and technical characteristics of complex technical systems, for example, to determine the number of parameters for monitoring the technical state of such systems.

The aim of the invention is to expand the functionality by determining the minimum amount of control parameters of a technical system with a total methodical probability equal to one.

The essence of the invention is that for determining the minimum set of monitored parameters, the technical system is represented as a directed graph. According to the functional model of the control object, the graph G is constructed (X, A). All arcs have directions corresponding to functional connections in the control object, the numbering of the vertices coincides with the numbering of the elements of the functional model. The solution of the problem of determining the minimum volume of monitored parameters is carried out on the basis of a structural analysis of the grapho-analytical model of the object of control. The graph G (X, A) is represented as an adjacency matrix:

if if an arc exists in G (X-Xj)

Oh, otherwise.

Based on the adjacency matrix, a reachability matrix R (V j-) is formed:

 1, if the vertex X / is reachable from .0, otherwise.

The set of vertices R (Xj) of the graph G (X, A) reachable from a given vertex X- is defined by the following expression:

R/

Vii

Where is the GFC.)

R (x ,.) f {Xjiur4x,) ur4Xi) u ... ur4x.)

the set of vertices reachable from vertex X when using a path of length j P is some finite number, (ijj 1, n), is the n-number of vertices of the graph.

The next stage of minimization is the analysis of the adjacency matrix by rows: the rows containing either only one unit or not containing units are determined, which corresponds to the mandatory set of functional

elements, the output of which is necessary to control the output signals.

At the following minimization stage, an additional set of functional elements is determined, after which it is necessary to control the output signals in order to eliminate non-distinguishable conditions. For this, the rows of the upgraded reachability matrix are compared in pairs. The upgraded reachability matrix is obtained by eliminating the columns of the reachability matrix, the numbers of which correspond to elements that are not waxed into the required set of functional elements, after which the output signals should be monitored.

The coincidence of at least two identical rows of the upgraded reachability matrix corresponds to the indistinguishability of the state of the control object by the corresponding elements. At the same time, an additional set of functional elements, after which the output signals need to be monitored, includes those elements whose state is indistinguishable, which were not included in the obligatory set of functional elements, after which the output signals must be monitored.

Thus, the minimum aggregate of monitored parameters is determined by combining the mandatory and additional aggregate functions. elements, after which it is necessary to control the output signals.

FIG. 1 shows the functional diagram of the device in FIG. 2 - with measures of the functional model of the control object; on fig.Z - graph G (X, A); figure 4 is the adjacency matrix A; FIG. 5 shows the reachability matrix R and the upgraded matrix R,

The device contains the device start-up input 1, the initial setting input 2, the generator of 3 clock pulses, the first 4 and second 5 elements AND, the first 6 and second 7 elements OR, the third elements AND, the third element OR 9, the trigger 10 , the third 11, the first 12 and the second 13 counters, the third 14, the first 15 and the second 16 decoders, the fourth element OR 17 ,. fourth 18 and fifth 19 counters, first block 20 of comparison, adder

21, the first element OR-NOT 22, the matrix of the fourth 23, -23 and fifth fifth elements AND, the field 25 of the set of graph of the functional model of the control object, the elements 26 26 of one-sided conductivity, the sixth elements AND, the second block 28 of the comparison, the seventh elements AND 29 9 ,, the second element OR-NOT 30, the eighth 31 and nine 32 elements AND, registers 33, -33, switching blocks consisting of the tenth 35 35 „p and the eleventh 36 - 36 | elements AND, adders 37, -37ц modulo two, the third element OR NOT

from the first inputs of the elements of the same name 8, -8j. In accordance with the inclusion of elements 26, they are recorded in accordance with the register bit 33, Thus, in register 33 / information will be recorded about the vertices of the simulated graph reachable from the first vertex.

10 For further operation of the device, a pulse is applied to the input 1 of the device. By this signal, trigger 10 is set to one state, the signal from trigger output 10 unlocks

15 element 4 and connects generator 3 to the first inputs of elements 5 and 24. The first pulse from generator 3 through open element 5 enters the first input of element 6, from the output of which

38, twelfth 39 and thirteenth 40, - 40p AND elements, (n + 1) -th register 41, fourteenth AND elements and display elements 43, -43 (k is a parameter of the structure of the graph corresponding to 20 of Pogo is recorded in counter 12. - the number of its associated vertices).

The device works as follows.

In field 25, in accordance with the topology of the graph representing the model of a system designed for control, include elements 26 in the conducting direction — between the 1st row and the jth column in the presence of a connection between the corresponding vertices of the graph. At the DL, the first cycle of the device operation determines the connectivity of the simulated graph by determining the reachability matrix. By applying a pulse to input 2, registers 41 are set to the zero state, counter 11 is set to state 1, the same pulse sets elements 12 and 13 to state 1 via elements 7 and 9, the first outputs of decoders 14, 15 and 16 a signal appears.

The signal from the first output of the decoder 14 opens the elements

35

40

8i-8,

and 27 h allows writing to registers,. The signal from the first 45 ° output of the decoder 14 turns off

The signal is output at the second output of the decoder 15. It is fed to the first input of the element 27, the second row of the dial pad 25 and the second column 23, - 23 of the matrix. Register 33 records information on reachability of BepntacH from the second vertex of the simulated graph. Further, on the first cycle, the device works in the same way.

When the pth pulse arrives at counter 12, a signal appears at the (n + 1) th output of the decoder 15 and at the overflow output of counter 18. This signal, through element 7, sets counter 12 to one state and is written to counter 11. the second cycle of the device.

At the second output of the decoder 14, a signal appears which, through element 17, opens element 5. The signal from the second output of decoder 14 opens element 32, connecting the output of block 20 to the second inputs of elements No signal at the transducer

40, -40

the decoder 15 enters the first input element 27, the output of which passes on the first column of floor 25, on the first row of floor 25 and on the first

FIELD 25 columns from the outputs of the decoder-. torus 15, as well as typed column columns from rows of floor 25 and prohibits writing to registers. C signal

from the first inputs of the elements of the same name 8, -8j. In accordance with the inclusion of elements 26, they are recorded in accordance with the register bit 33, Thus, in register 33 / information will be recorded about the vertices of the simulated graph reachable from the first vertex.

For further operation of the device, a pulse is applied to the input 1 of the device. By this signal, trigger 10 is set to one state, the signal from trigger output 10 unlocks

element 4 and connects generator 3 to the first inputs of elements 5 and 24. The first pulse from generator 3 goes through the open element 5 to the first input of element 6, the output of which is written to counter 12.

Rogo is recorded in counter 12.

° output of the decoder 14 turns off

The signal is output at the second output of the decoder 15. It is fed to the first input of the element 27, the second row of the dial pad 25 and the second column 23, - 23 of the matrix. Register 33 records information on reachability of BepntacH from the second vertex of the simulated graph. Further, on the first cycle, the device works in the same way.

When the pth pulse arrives at counter 12, a signal appears at the (n + 1) th output of the decoder 15 and at the overflow output of counter 18. This signal, through element 7, sets counter 12 to one state and is written to counter 11. the second cycle of the device.

At the second output of the decoder 14, a signal appears which, through element 17, opens element 5. The signal from the second output of decoder 14 opens element 32, connecting the output of block 20 to the second inputs of elements No signal at the transducer

40, -40

° output of the decoder 14 turns off

FIELD 25 columns from the outputs of the decoder-. torus 15, as well as typed column columns from rows of floor 25 and prohibits writing to registers. C signal

the inputs of the first column of the element-gg matrix of the first output of the decoder 15 posts 23 ih connecting the outputs of the columns of the input field to the corresponding inputs of the register 33. The c-output signal of the first column is recorded in the first register bit 33. In accordance with the inclusion of elements 26 in the first row of field 25, the signals are recorded in the corresponding register bits 33i. The same signals are fed to the first row of the field 25. In accordance with the topology of the graph, the inputs of the adder 21 are given signals corresponding to the number of arcs extending from the first vertex. At the output of the adder 21, a number is generated in the binary parallel code corresponding to the number of arcs exiting the first vertex. The signals from the output of the adder.

The first output of the decoder 15 enters the first row of the floor 25. In accordance with the topology of the graph, the inputs of the adder 21 are given signals corresponding to the number of arcs extending from the first vertex. At the output of the adder 21, a number is generated in the binary parallel code corresponding to the number of arcs exiting the first vertex. The signals from the output of the adder.

except for the low bit, the inputs of element 22 are received. If there is no arc or only one arc from the first vertex of the simulated graph, then the low bit output; adder 21 is 1 or O, and all other outputs are O. In this case, at the output of element 22, a signal is formed, which through the open element 32 enters the second inputs of the elements, and opens them. The signal from the first output of the decoder 15 is fed to the first input of the element 40, and is recorded in the first register bit 41, which corresponds to the inclusion of the first functional element of the controlled system in the mandatory set of

controlled parameters.

When recording the next pulse from the generator 3, a signal appears at the second output of the decoder 15, which is fed to the second

the string FIELD 25 and the first input of the element 40 ,. If no more than one rectifying diode 26 is included in the second row of the keypad, a signal is generated at the output of block 20 that permits writing the unit to the second register register 41. Then, in the second cycle, the device works in the same way. When a signal appears at the (n + 1) th output of the decoder 15, a signal is generated at the control output of the overflow of counter 18, which is written to counter 11 and through element 7 sets the counter to 12 to 1. This corresponds to completion

the second cycle of operation of the device is placed in the upgraded matrix R, the beginning of the third, on which it determines, at the same time, at the output of element 38 for the entire additional set of monitored parameters in order to eliminate indistinguishable states of the object of control.

In the third cycle of operation of the device, a signal appears on the third output of the decoder 14, which opens element 24, connecting the counter 13 to the output of element 4, the signal from the third output of the decoder 14 also goes to the second input of element 31, connecting the output of element 30 to the first input of the element 39. The counter 13 is set to state 1, at the first outputs of the decoder 15 and 16 there are signals that go to the first and second inputs of the elements 29., - 29 and to the first inputs of the elements 35 35. | p,

 -Tws

block 34, respectively.

0

0

The signal from the output of element 29. enters the first input of element 30, on whose output a low potential is established and closes elements 31 and 34, prohibiting writing to register 41. This eliminates the possibility of changing the contents of register 41 when comparing the row of the upgraded reachability matrix R itself with myself. The next clock pulse through elements 4 and 24 is recorded in counter 13, at the second output 5 of the encoder 16 a signal appears that goes to the 1 second input of the element 29 and to the first inputs of the elements 3621-365 of the block 34.

The second inputs of the AND elements of each block 34., - 34 "receive information from the corresponding register bits 41. The first and second inputs of the corresponding adders receive the elements of the first and second rows of the upgraded reachability matrix R, respectively. If at least one of the columns of the upgraded matrix R elements of the first and second lines do not match, then the output of element 38 is set to zero potential, which is fed to the second input of element 39, the zero signal from the output of which is fed to the second inputs of elements 4 0., - 40, and not

g permits writing to register 41. If, on all columns of the upgraded matrix R, the elements of the first and second rows are the same, then the first column of the reachability matrix R including

five

The signal that opens the element 39, the signal from the output of which opens the elements 40, is 40. An entry is made to the first bit of register 41: if a unit was recorded in the first bit of register 41, the information in it does not change. Next, the device works in a similar way.

When a signal appears at the (n + 1) th output of the decoder 16, a signal appears at the overflow output of counter 19, which through element 9 sets counter 13 to state 1, and through element 6 it increases the content of counter 12 by one, at the second output of the decoder 15, a signal appears.

the first input of element 29 and the first inputs of elements., block 34. The signal from the first output of the decoder 16 is fed to the first inputs of elements 36 36 ;, and to the second input of the element. Next, the second row of the upgraded reachability matrix R is compared with all rows this

matrices. I

At the onset of a signal at the output of the decoder 15, a signal appears at the overflow output of the counter 18, which, through element 7, sets the counter 12 to the state 1 and increases the content of the counter 11. At the fourth output of the decoder 14, a signal arrives set in the trigger 10, a zero signal from the output of which locks the element 4 and disconnects the generator 3 from the device. In addition, the signal from the fourth output of the decoder 14 enters the second inputs of the elements, the first inputs of which receive information from the outputs register and 41. slyuchayuts sootvetstvuyugtsye MeHTbi element 43 that indicates the inclusion of the corresponding parameter in the minimum volume control parameters technical state.

Claims (1)

Invention Formula A device for determining the size of a sample of control parameters, containing a clock pulse generator, the first, second, by the number n of vertices of the graph of the functional model of the object of control, third, and a matrix of php fourth elements And, the first decryptor and the first counter, n registers , the field of the graph set of the functional model of the control object and the number k of connected vertices of the graph of the functional model of the control object k of unilateral conductivity elements, the output of the first counter is connected to the input of the first decoder, the first input and output of And are connected respectively to the output of the clock generator and the first input of the second element, AND, the rows of the set of the graph of the functional model of the control object are connected with its columns in accordance with the topology through the elements of one-sided conductance the graph of the functional model of the control object, the rows of the set field of the graph of the functional model of the control object are connected to the outputs of the third elements of the same name and the outputs of the fourth elements and the i-th column of the matrix are connected to the inputs of the same name of the i-ro regisfra, expanding the functionality of the device by determining the minimum amount of control parameters of the technical System, it contains the second decoder and the second, third, fourth and fifth counters, the third decoder, five, five sixth, twelve The thirteenth, and thirteenth fourteenth elements AND, six OR elements, n modulo two adders, the first OR OR NOT element, (n + O th register, trigger, n indication elements, the first comparison block containing the adder, the second element OR-NOT and the ninth element AND, as well as the second unit of comparison, which includes the fifth seventh elements AND, the third element OR-NOT and the eighth element AND, and, moreover, the second commutation blocks, each of which consists of the fifth and fifth eleventh elements And the output of the second counter is connected to the input of the second decoder, counting inputs The third and fifth counters are connected to the same outputs of the first and second decoders, respectively, the input of the third decoder is connected to the output of the third counter, the output of the first element I is connected to the first input of the fifth element I, the second input and output of which are connected respectively to the third output of the third decoder and the counting input of the second counter, the installation input connected through the third element OR to the installation input of the device, also connected via the second element OR and directly to the installation input respectively the first counter and the third counter, as well as to the inputs of the installation in О registers, the counting input. The third counter is connected to the overflow output of the fourth counter and the second input of the second element OR, the single input and output of the trigger are connected respectively to the device start input and the second input of the first element AND, the first output of the third decoder OR to the first input of the third AND elements, recording resolution entries of all registers except (n + 1) -th, and the second inputs of the sixth AND elements, the second output of the third decoder is connected to the second input of the Fourth element OR and the second input The ninth element And, the third output of the third decoder is connected to the second input of the eighth element And, the fourth output of the third decoder is connected with the zero input of the trigger and the second inputs of fourteen elements B And, the output of the fourth element OR is connected to the second input of the second element AND the output connected to the second input of the first element OR, the output and first input of which are connected respectively to the counting input of the first (the counter and the overflow output of the first counter, also connected to the second input of the third element The input of each sixth AND element is connected to the corresponding output of the first decoder, and the output is connected to the corresponding column of the set field of the graph. functional model of the control object, the second input of the corresponding third element AND, the first input of the fourth element AND of the corresponding row of the matrix and the corresponding input of the adder The outputs of the bits of which, in addition to the low-order bit, are connected to the inputs of the first element SH-NOT, the output of which through the ninth element I is connected to the second inputs of the thirteenth elements I, connecting yuchennyh outputs to the corresponding inputs of the (n + 1) -th register, and the first inputs - to the corresponding outputs of the first decoder, to the first inputs of the tenth elements And the corresponding switching blocks and the second inputs of the fourth elements And the corresponding columns of the matrix, the first, second input and output of each seventh element And connected respectively with the corresponding output of the first decoder, the corresponding output of the second decoder and the corresponding input of the second element OR — NOT, the output of which through the eighth element AND is connected with the first input of the twelfth element AND, the output and the second input of which They are connected respectively to the second inputs of the thirteenth elements AND and the output of the third element OR NOT connected by the inputs to the outputs of the corresponding modulo-two adders, the output of the bits. The (n + 1) -th register is connected through the corresponding fourteenth elements AND to the inputs of the corresponding elements indication and directly - with the second inputs of the corresponding tenth and eleventh And elements, the third inputs of which are connected to the outputs of the corresponding bits of the corresponding registers, the first inputs of the eleventh elements And each switching unit coupled with a corresponding, vpsodom second decoder, the output of each of the tenth and eleventh each element and all the switching units are respectively connected to first and second inputs of the respective summing block modulo two ... s.o % J 2 X; XiXjX X5X "l Fi & XiXzXyXfXsXsX7} (s FIG 3 AWjx X5XtfX7 f