SU1406789A1 - Reversible counter - Google Patents

Abstract

The invention relates to computing and can be used for reversing the counting of pulses, moving the working bodies of machine tools equipped with pulse sensors with displacement sensors, in devices for calculating the difference in the number of objects that have passed in opposite directions. The aim of the invention is to simplify the device. A reversible counter contains in each bit an element KII 1, a counting trigger 2, and an element 3. The inverse output of the counting trigger 2 is connected to the first input of the element I 3 on each bit. The second inputs of all elements AND 3 are combined and are the first input 4 of a reversible counter, the second input 5 of which is the combined first input of the element OR 1 and the input of the counting trigger 2. The output of the element OR 1 is connected to the first input of the element OR 1 and the input of the counting trigger 2 next bit The output of the FM element is connected to the second input of the element OR I in each bit of the counting trigger, whose codes are the direct outputs of the counting trigger 2. Pulses to inputs 4 and 5 should be fed alternately. 1 il. C (L

Description

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The invention relates to computing and can be used for reversing the counting of pulses, the movements of the working bodies of machines equipped with pulse displacement sensors, in devices dp of calculating the difference in the number of objects that have passed in opposite directions.

The aim of the invention is to simplify the device.

The drawing shows a functional diagram of the reversible counter.

The reversible counter contains the elements OR 1, the counting triggers 2, the elements AND 3 in each discharge. The counter has the first 4 and second 5 inputs and outputs 6.

Reversible counter works as follows.

In the initial state, the signals at inputs 4 and 5 are absent, and all the triggers 2 are set to the zero state. The duration of the signals from inputs 4 and 5 must be greater than the duration of the transient processes in the counter bits. When a pulse appears on the first input 4, all counting triggers 2 located after the first trigger 2 set to O are switched to the inverse state. Then, when a pulse appears on the second input 5, all counting triggers 2 are switched to the inverse state. Thus, the reversible counter counts in the forward direction.

When a pulse occurs, first, at the second input 5, all counting triggers 2 are switched to the inverse state. Then, when a pulse is detected at the first input 4, the counting triggers 2, located after the first trigger 2, set to o, switch to the inverse state. Thus, the reversible counter counts in the opposite direction (subtraction mode).

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Pulses on the first 4 and second 5 inputs should not appear at the same time. In case counting trig0

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When 2 are switched on the leading edge of the signals, then to eliminate races it is necessary that the speed of the element OR 1 exceeds the total speed of the trigger 2 and the element AND 3 of each digit of the counter. When switching triggers 2 on the falling edge of the signals, the mutual response of the elements of each bit is not regulated. The occurrence of an even number of pulses at any input of a reversible counter does not change its state, if at an atom no pulses arrive at another input.

The use of the proposed reversible counter is effective in devices for counting objects moved by the conveyor in two directions and to avoid false counting due to fluctuations in the conveyor.

Claims (1)

Invention Formula A reversible counter containing in each bit the OR elements and counting triggers, the inverse outputs of which are connected to the first inputs of the corresponding elements AND, the forward outputs of the counting trigger are the outputs of the reversing counter, the second input of the AND first element of the first bit is the first input of the reversible counter The first input of the OR element of the first bit is the second input of the reversible counter, characterized in that, in order to simplify the reversible counter, the second inputs of the AND elements of each bit are combined between each other. first, the input of the counting trigger of the first bit is uniform with the first input of the element OR of its bit, the output of the element OR of each bit is connected to the first input of the element OR of the subsequent bit and with the input of the counting trigger of the subsequent bit connected to the second input of an OR element of the same bit. uh  T t1 L l I 1: „J1j.zZ  /