SU1396147A1 - Device for interfacing a computer with peripherals - Google Patents

Abstract

The invention relates to computing and can be used to build standardized interface devices, for example computers with various objects. The aim of the invention is to improve the performance of the device. To this end, a device containing a clock, the first element I, the first counter, the sync pulse decoder, the first trigger, the delay element, the three groups of switching elements, the address register, the two address decoder, two memory blocks, the multiplexer group, the output register, a group of counters, a reception register and a issue register, a group of shift registers, a second trigger, a second AND element, a second counter, and a gold element are NOT .. 2 Il. with

Description

with so about:

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I The invention relates to a computational frenbHoft technique and can be used to build a unified interface device, for example, a computer with various objects.

The aim of the invention is to improve the performance of the device.

Figure 1 shows the functional: the scheme of the device; Figure 2 shows the time diagrams of his work.

I Interface device contains (1 clock pulse generator, Element I 2, first counter 3, decipher-A clock sync pulses, first trigger 5, delay element 6, output 7 acknowledgment rate, I reset input, 9 start sign , elements: 1 P ,,,,,, About, and 11 ,,,,. ,, 1 1, switching the first and second .fj regC1 p 12 addresses, the first register 13 addresses, the third memory block 14 memory, cartoon) plex 15,.,. ,,, 15, output register 16j, 1 7 ,,, ..., 7 jj + j elements of the Iuta1 and the third group, the second decoder 18 addresses, the second block 9 pa , counters 20 ,, „,, 20 groups, register 2 receptions, reg Istr 22 issuance, | ain 23j ,, o ,. , 23 | at the gruggga of the outputs of the soio device, the second |; 24, bus 25, ,,, “., 25 groups} of BHe control strokes, reconciled computer, 26 computer mode control, (27 computer recording, tires 28 ,, „,,, 28 for a group of informational computer outputs, tires for 29,„,., 29ts groups (information inputs of external) oystv, region 30, „.., 3Dp groups of information outputs of external devices, actions 31, ,, ,,., ,, 31 into groups of informational-tgk outputs of the nuclear, gangs 3,,. ,, 3. groups of command inputs of external devices, registers 33 ,,, „, 33 f, shift groups, second trigger 34, the second element And 35 and ale T is not 36,

The device works as follows about & at once.

Elements 10, 1 and 17 are switched by the signal from input 26, and memory block 14, depending on the value of this signal, operates in the recording mode 1 or read out. Before starting the operation of the device, it is necessary to write into the memory block 14 information about the algorithm of the device operation and the cycle of the exchange of the connected devices, and to the memory block 19 the constants to control the counters 20 in

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work process. For this, signals O are sent to inputs 26 and 9, as a result of which the device is set to recording mode, and the passage of pulses from generator 1 through element 2 to the inputs of counter 3, registers 33 and trigger 34 is prohibited. Elements 10, 11, and 17 of the commutator switch the outputs of the counter 24 and the address register 17, respectively. The signal from the input Z leads triggers 5 and 34, counters 3 and 24, and register 16 to the initial position. Then, at the input 27, the recording resolution signal is set, and at the inputs 8 and 9, the signals 1. At that, the pulses from the generator 1 through the element 2 come to the input of the counter 3, from whose output the number of counted pulses is transmitted to the input of the decoder 4 As a result, from the output of the decoder 4 to the input of the register 12, a pulse arrives at which the address from the output of the counter 24 is written to it. Since the counter 24 was preset to zero, the first address will be zero. The address is decrypted by the I 3 and 18 decoders and in cells 4 and 19 of the memory a cell is selected into which the information from the device 28 input is to be written. Counter 3 continues to count and the signal from the decoder 4- sets the trigger 5 to one state. In this case, a reference signal is supplied to the memory blocks 14 and 19, and the input from the 2R input is written to them at the specified address. Then the signal from the decoder 4 sets the trigger 5 to the initial state, which prohibits accessing the memory blocks and signals the computer to output new information to the input 28 on the output (bus) 7. At the same time, this signal adds one to the contents of the counter 24 and through the delay element 6 sets the counter 3 to the initial state. Further, the process is repeated several times until all the constants necessary for controlling the counters 20 are written to the memory blocks 14 and 19. Then, the write enable signal from input 27 is removed, allowing recording only to memory block 14. After this, the described process is repeated again, and the information on the operation algorithm of the device and the cyclogram of the exchange of the associated devices (inside the cycle) are recorded in the memory 4. The previously recorded information in the memory block 14 is erased. Introduction to the structure of the counter 74 allows you to simplify the recording of information in the memory blocks and exclude the inputs of the address from the computer. Upon completion of writing to memory block 14, input 1 is given a signal 1, permitting the connection from memory block 14, and switching elements 10, 11 and 17 switch at the same time the outputs of group multiplexers 15 and the corresponding groups of outputs of register 16 respectively. - pulse signal Q to input 8, driving counter 3, triggers 5 and 34, and register 16 to the initial state.

The process of reading information from memory blocks 14 and .19 is similar to the writing process and is controlled by the generator 1, counter 3, depiffrator 4 and trigger 5. The read addresses from memory block 19 are determined by signals from the first output of register 16. Address The readings from memory block 14 are determined by a set of signals at input 23, transfer outputs of counters 20 and the corresponding output groups of register 6. These signals are input to register I2 through switching elements 11 and 10, respectively, from outputs of register 16 and typlexors 15 which can switch inputs in arbitrary order. This is achieved by the independence of the control inputs of each multiplexer 15 from each other. Therefore, when changing the interfaced devices, the external input signals of the interface device at the inputs 23 of the multiplexers 15 will not need to be re-switched.

The output signals of the memory unit 14, which are fed to the input of the register 16, pealize the output functions of the control unit. These include the address of the constant in memory block 19, the signals for putting the constant into counters 20, the signals for controlling the mode and recording information in the receive registers 21 and 22 bits of information, the command signals of the interfaced devices (bus 32), the control signals for multiplexers 15 and the code the next state, coming to the inputs of the switching elements 11. All this information is entered into register 16 by a signal from a decoder 4. By the same signal, information

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From the group of tricks of the memory block 14 is entered into the group of shift registers 33. : The pulse, the input of the register 3 into the parallel information input mode, is triggered by the trigger 34 and the AND element 35 and is equal to the duration of one period of the frequency G of the generator pulses 1. The information in the registers 33 is entered on the front of the sync signal from the output of the HE element 36, after which as the clock decays, the registers 33 switch to the shift mode, and the information begins to shift at a frequency f. Fig. 3 shows the time diagram of this process. The length of each register of the 33 groups is equal to f / F, where F is the frequency of the signals from the decoder 4. The cycle time of the automaton Td 1 / F, therefore, any pulse (or a group of pulses) can be received inside the clock at the outputs 25 of the device the discreteness of the change of its (their) location is equal to the period of the frequency f of the generator 1. Thus, a cyclogram of information exchange with a high-speed device (for example, semiconductor nuclear power, etc.) can be organized in one or two device operation cycles. For slower-acting devices (for example, external y), a cyclogram can be organized by setting the corresponding time intervals on blocks 19 of memory constants in counters 20. Discretization of the installation of cyclograms at the same time (via bus 32) will be I / F, since the counters 20 is considered with the frequency F. The accuracy of the installation of the time sequence diagram on the outputs 25 can be increased by increasing the frequency f and increasing the width of the registers 33, while leaving the frequency F unchanged.

Information is exchanged between the associated devices through the receive and issue registers 21 and 22. One of the devices (for example, a computer) sends information from outputs 28 to register 22, then it enters another device (for example, an external memory) via outputs 29. Information can be transferred back from inputs 30 to register 21 and then to device 31 . Registers 21 and 22 can, by command from register 16, switch to information shift mode and repack data into

various formats. In addition, they can be used as a buffer memory to equalize the rate of inormation exchange between devices with different speeds.

Claims (1)

Isoyretia formula A device for interfacing a computer with; external devices containing the generator: clock pulse, first element I, first counter, decoder; clock pulses, first trigger, elec: delay element, three groups of elements: switching, address register, two address decoders, two memory blocks,: a multiplexer group, an output ryo; a gist; a group of counters; a receive register and a issue register, the first; And the second inputs and the output of the first element I are connected respectively to the output of the clock pulse generator; Owl, device inlet for connection and to the output of the computer and starts working: the clock input of the first counter: first and second inputs and a reset output; which podklyuchezchy respectively to the output of the delay element, entry mouth | roystva for coupling to the output to the input is responsible w apparatus : neither the initial conditions of an unified computer and the input of the clock encoder of the clock pulses, the setup input, the counting input and the reset input of the first trigger are connected according to: The first and second outputs of the clock decoder and the input of the dp connection to the output of the initial conditions The computer, the input of the delay element is connected to the second output of the Decoder of the clock pulses and is the input of the device for connection to the output of the readiness of the computer, all the cells of the switch, the first and second groups are connected respectively to the first and second info The main inputs of the address register, the synchronous input. Which is connected to the third output;) the sync pulse decoder, the input and output of the first address decoder are connected respectively to the output of the address register and the address input of the first memory block, the information input, the reset input and the vertical input of the output register, respectively. to the first output of the first memory block, the input of the device for connecting to the output of the job the initial ones: the conditions of the computer and the fourth output of the de-racter of the clock pulses the inputs and outputs of the transfer of the group counters are connected respectively to the fourth output of the decoder of clock pulses and the first information inputs of the multiplexers of the group, the second information inputs of which are connected to the inputs of the device for connection to the outputs of the external devices, the first information inputs of the switching elements of the first group are connected to the outputs of the multiplexers of the group, the write / read input of the first memory block and the control inputs of the switching elements of the first, second and third groups are connected to the input devices for connecting to a computer mode control output, the first and second information inputs of the switching elements of the third group are connected respectively to the output of the address register and the first information output of the output register; the input and output of the second depressor of the address are connected respectively to the outputs of the switching elements of the third group and the address input of the second a memory unit, a write / read input and a voucher resolution input of which are connected connections to the control output of the computer and the output of the first trigger, the information inputs of the first ii second memory blocks and the information input of the register are connected to the inputs of the device to connect the information outputs of the computer, the synchronous input, the shift control input and the output of the output register are connected respectively to the first and second characteristic outputs, output register and device outputs for connection to information inputs of external: x devices, account resolution inputs and information inputs of the group n dklyucheny respectively to the second output data output PE. the hystera and the output of the second memory block, the information input, the sync input, the shift control input and the output of the receive register are connected respectively to the device input for connecting external information devices to the information output group, the third and fourth sign outputs of the output, register and device output for connecting data computer inputs, the third info output output register is you 71 device for connecting to the external device command terminals, a quarter and five information outputs of the output register are connected respectively to the control inputs of the group multiplexers and the first information inputs of the switching elements of the second group, characterized in that, in order to improve performance, it contains the group of shift registers, the second trigger, the second element AND, the second counter and the element NOT, while the information inputs, synchronous inputs, the inputs for controlling the operation mode and the outputs of the group shift registers The plugs are connected respectively to the second output of the first memory block, the output of the NOT element, the output of the second element AND, and the outputs of the device for connection to the outputs of external devices, the first input of the second element AND is connected to the fourth output of the clock pulse sync controller. 0 6 five 147. 8  Form P, input, input, sync input and inverse n output of the second trigger are connected respectively to the fourth output of the si-hroytulsov, device input for connecting to the output of the initial conditions, the computer, the output of the first element And the second input of the second element the element is NOT connected to the output of the first element I, the reset input, the clock input and the first and second information outputs of the second counter are connected respectively to the input of the device for connecting to the output of setting the initial conditions of the computer, the second the output of the decoder and clock inputs informatsionnm second switching elements of the first and the second group, and third and fourth data inputs of the multiplexers are connected respectively to the group schi- hydrochloric zero potential and the tire building unit of the device.