SU1624330A1 - Device for slippage measurement - Google Patents

Abstract

The invention relates to a measurement technique and can be used in research and production laboratories for recording slip values of asynchronous motors during a run. The aim of the invention is to improve accuracy. The values are recorded in such a way that the values of the rotation speed of the monitoring object's rotor are recorded in the external memory block 21 in direct access mode, and the network frequency values in the main memory block 25 in the mode of software polling of the informative signal. The operation of the device and the processing of the registered values is controlled by the processing unit 23. The device has increased the size of the counters 7 and 11 of the rotation speed measurement channel and the corresponding data bus 1 or

Description

The invention relates to measuring equipment and may find application in research and factory laboratories for recording slip values during the take-off run. 5?

The aim of the invention is to improve the accuracy of measurement.

The drawing shows a structural diagram of the device.

A device for measuring slip 10 comprises a frequency driver 1, a counting trigger 2, a pulse generator 3, a rotational speed sensor 4, a counting trigger 5, circuit I 6, counter 7, bus formers 8 and 9, circuit I 10, meter 11, 15 bus shapers 12 and 13, RS flip-flops 14-17, direct memory access controller 18, parallel interface 19, programmable timer 20, external memory unit 21, as well as the system bus 22, which is part of the processing unit 23, in which also includes the Central processor 24, block 25 RAM and block 26 display information.

A device for measuring slip 25 operates as follows.

When a power supply is applied to the device, the central processor 24, in accordance with the initialization program, performs programming of the external 30 blocks in such a way that the direct memory access controller operates in the same priority mode as the inputs, the boundaries of the memory areas are set as high as possible (16 kbytes in each area). 35 The parallel interface 19 is programmed so that channel A operates in output mode and channel B in input mode. The counters STO, CT1 of the programmable timer 20 are set to interrupt the terminal count 40, the counter ST2 of the programmable timer 20 and channel C of the parallel interface are not involved. When a control object is connected to the network through the zero bit of channel A 45 of the parallel interface 19, the level 1 at the input is set. Direct access permission of the controller 18. The process of registering values begins.

The first pulse received at clock input 50 from trigger 5 will translate it into a state opposite to the initial one, for example, from 0 to 1. Through circuit I 6, pulses from the output of generator 3 will arrive at the input of counter 7 over a period of time, allocated by the period of the informative signal.

The second pulse received at the input of trigger 5, will translate it into state 0. The pulses from the output of the generator 3 through the circuit And 10 will go to the output of the counter

11. The counter 7 stops working and the number m _ 1p1 _ 60 ^Np1 ~ ““ φΓΓζ · To 'is found in it where T _P 1 is the first value of the period of rotation of the rotor of the test object;

That ~ period of pulses of the generator 3;

p _R 1 - the first value of the rotational speed of the rotor of the control object;

Ζ is the resolution of the speed sensor.

The voltage drop at the input 30 of the direct memory access controller 18 will cause a request. At the same time, the RS flip-flop 14 will be transferred to state 0. The bus driver 8 will exit from the third state and the high byte of information fixed by the counter will be installed on the data bus of the controller 18. The end of the recording process will be indicated by level 1 ”at the output of Direct Access Confirmation (software). By this signal, trigger 14 will go to state 1, bus driver 8 to the third state, information from the data bus will be removed, trigger 15 will go to zero, bus driver 9 will exit the third state and the least significant byte of information will be installed on the data bus of controller 18 fixed by counter 7. At the same time, a direct memory access request will be called up at input 31 of the controller. The end of the recording of information in the block 21 of the memory will indicate the level of "1 at the output of the PT controller 18. This indicates that the whole number Ν _ρ ι written in the block 21 of the memory. According to this signal, trigger 15 will go into state 1, bus driver 9 - into the third ”state, information from the data bus of the direct memory access controller 18 will be removed, counter 7 will be reset and prepared for a new recording cycle.

The third pulse received at input C of trigger 5 will again transfer it to state 1. At the same time, counter 7 will start working, and the number 11 will be fixed in counter 11

N _P 2 = = ---- then — γ-, ^p To p _p 2 · Ζ T _about where T _P 2 - the second value of the period of rotation of the rotor of the control object;

p _R 2 - the second value of the rotational speed of the rotor of the control object.

Level 1 at input 32 of the direct access controller 18 will cause a request for a second input. At the same time, trigger 16 will go into state 0, bus driver 12 will exit from the third state and the highest byte of the number N _P 2 will be installed on the data bus of controller 18. Level 1 at the output Direct access confirmation (P2) will indicate the end of pro! the process of recording information in the block 21 of the memory. This signal will switch trigger 16 to state 1, bus driver 12 will go into the third state, information from the controller data bus will be removed, 1 trigger 17 will go to zero, bus driver 13 will exit from the third state and the low byte will be set on the controller bus 18 Np2 numbers. At the same time, a request for recording information at the input 33 of the controller 18 will be called up. Level 1 at the output of the PZ of the controller 18, indicating the end of the recording process, will set the trigger 17 to state 1. The bus driver 2 will go into the third state and the information from the data bus controller will be removed. The same signal counter 11 will be reset to zero and prepared for a new cycle of work.

The first pulse received at the clock input C of the trigger r ^ will translate it into a state opposite to the original one, for example, state 1. Level 1 will be set at the enable input P of the first counter CT1 of programmable timer 20 and this counter will begin to register the generator pulses during the time determined network period.

The second pulse received at the clock input C of trigger 2, will translate it into state 0. The counter STO of the programmable timer 20 will start working, and the number ST1 will be fixed in the counter

Nd = ½ ¹ >

about where Tci is the period of the first pulse of the network.

The central processor 24 continuously polls the level of the signal installed at the enable input P of the zero counter of the SRT programmable timer 20 and at the zero-input of channel B of the parallel interface 19. As soon as the input is set to level 1. the central processor 24 writes to the block memory 50 25 23 processing the value of Nd. registered by the counter CT1 of the programmable timer 20 and, having reset the counter, returns to the polling of the signal.

The third pulse received at the clock input 55 of trigger 2, will translate it into state 1 ”. The CT1 counter starts to work, and the number m ^Tg Nci - appears in the SRT counter.

¹ about where T _C 2 - the second value of the network period.

As soon as the level 0 ”is set at the input of the zero discharge> channel B of the parallel interface 19, the central processor 24 will rewrite the number N _C 2, registered by the counter of the SRT programmable timer 20, into the memory of the processing unit 0 then, after which the counter is reset. returns to polling signals.

The process of registering values continues until all of the external memory of block 21 is full. After this 5, the direct access controller 18 is turned off and the level 0 is set at the bus capture output. Central processor 24, with each cycle of writing to the memory of block 23, polls this signal, at 0 the actual value stops recording the values of the network period and starts processing the results using the formula

S = 100% = (1 - ^) 100% = ⁼ > · ^100% ' ^{, 00%} 2Q where N _C j - je value characterizing the network period;

Npi - i-e value characterizing the period of rotation of the rotor;

Z <p- resolution of shaper 1;

Resolution 4 speed sensor.

The values of Ν _ρ ι are taken sequentially, with several values of Ν _ρ ι corresponding to ₄ q corresponding to the same value of N _C j. The sequence of sampling values must be performed in accordance with the condition

Στ _Ρ ι <Td i = 1 k

Σ Tpi <Tc2 etc.

t, η + 1

The values recorded and processed are displayed on the information display unit 26 in the form of tables, graphs, individual values at the request of the operator.

Claims (1)

Claim A device for measuring slip, containing a speed sensor, a frequency driver, two counting triggers, two counters, a pulse generator, two I circuits, four bus drivers, four RS triggers, a controller Ί direct access to memory and a processing unit, consisting of a central processor, random access memory, information display unit and the system bus connecting them, while the output of the speed sensor is connected to the input of the first counting trigger, the direct and inverse outputs of which are connected to the first inputs of the first and the second circuit And, respectively, the second inputs of which are connected to the output of the pulse generator, and the outputs with the counting inputs of the first and second counters, respectively, the outputs of which are connected to the inputs of the first and For the first bus shapers, respectively, the outputs of all bus shapers are connected by a data bus to the input of the direct memory access controller connected to the system bus of the processing unit, while the enable inputs of the first, second, third, and fourth bus shapers are connected to the outputs of the first, second, third, and fourth RS-flip-flops, respectively, the reset inputs of the third and fourth RS-flip-flops are connected to the first and second confirmation outputs of the direct memory access controller, respectively, while q the frequency shaper of the network is connected to the input of the second counting trigger, characterized in that, in order to increase accuracy, an external memory unit, a parallel interface and a programmable timer are introduced into it, while the inverse and direct outputs of the first counting trigger are connected respectively to the reset inputs of the first and the second RS-flip-flops and with the first th second inputs of the request of the controller of direct access to memory, the third and fourth inputs of the request of which are connected to its first and second confirmation outputs, respectively, and the third and h the fourth confirmation outputs are connected respectively to the installation inputs of the third and fourth RS triggers and the reset inputs of the first and second counters, the second outputs of which are connected to the inputs of the third and fourth bus drivers, respectively, while the installation inputs of the first and second RS triggers are connected respectively to the reset inputs of the third and fourth RS triggers, the external memory block is connected by the first bus to the system bus of the processing unit, and the second bus is connected to the direct memory access controller, permission input it is connected to the output of the parallel interface, the first input of which is connected to the capture output of the direct memory access controller, and the second input is connected to the inverse output of the second counting trigger and to the first enable input of the programmable timer, the second enable input of which is connected to the direct output of the second counting trigger, moreover, the first and second counting inputs of the programmable timer are connected to the output of the pulse generator, and the parallel interface and programmable timer are connected to the system bus unit processing.