SU1383357A2 - Priority device - Google Patents

Abstract

The invention relates to computing technology, in particular, to devices for priority service of requests, and can be used in devices for interrupting electronic computers in order to provide variable priority with interrupt signals. The purpose of the invention is to expand the functionality of the device through the organization of variable priority, both forced and automatic. This is achieved by introducing into the device a group of display elements, two OR elements, two counters, a trigger, two pulse formers of delay element 26, element AND 25, a group of 30 pulse formers, a group of 31 delay elements. Dryness of the invention consists in the possibility of changing the priorities of each channel automatically at certain intervals, the duration of which can be controlled by setting different accumulative capacity of the second counter, the possibility of forced, i.e., manual changing of channel priorities by the operator, as well as the possibility of observing for changing priorities. 1 il. (ABOUT

Description

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The invention relates to computing, in particular, to devices for priority service of requests, can be used in devices for interrupting electronic computers for the purpose of providing variable priority with interrupt signals, and is an improvement of the device according to the author. St. No. 1137468.

The purpose of the invention is to expand the functionality of the device through the organization of variable priority, both forced and automatic.

The drawing shows a block diagram of the device.

The device contains a group of triggers 1 request, a group of priority registers 2, a group of comparison circuits 3, a group of elements AND 4, elements OR 5 and 6, a prohibition element 7, a generator of 8 clock pulses, an element 9, a counter 10, a control trigger 11, an element 12 delays, input request groups 13, reset 14 and information 15, start input 16, signal output 17, request source identification output group 18, request display group 19, OR element 20, counter 21, pulse driver 22, trigger 23, input 24 These blocking element And 25, the element 26 delay stroke 27 automatically changes the priority, the counter 28, pulse generator 29, a group of pulse shapers 30, group delay element 31, an OR gate 32, an inlet 33 the lock.

The device works as follows.

In the initial state, the triggers 1, 11 and 23 and the counters 10, 21 and 28 are in the zero state, and in registers 2 the priority codes are written. In this case, the source of the request of the highest priority corresponds to the smallest binary code.

Requests from sources in the form of pulses at random times arrive at inputs 13 and translate the corresponding triggers 1 into one state, preparing the elements AND 4 to trigger. The pulse signal from the output of the element OR 6 puts the counter 10 into the zero state and through element 12 delays in a single state trigger 11. The unit potential from its direct output opens the second input of an element 9, allowing the passage of clock pulses from the generator output of 8 clocks through an element 9 to the counting input of the counter 10, to the out Which begins to form an incremental sequence of codes of binary numbers, which are fed to the second inputs of the comparison circuits 3, the first inputs of which are affected by the priority codes from the outputs of the registers 2. The same codes are fed to the inputs of the corresponding display elements 19, on which the digit is highlighted, equal to the corresponding code priority.

When the codes coincide, the output of the circuit 3 forms a single signal, which

can go to the output of the corresponding element And 4 only if the corresponding trigger 1 is in the unit state. A single signal from the output of the AND 4 element arrives at the corresponding output 18, identifying the source of the request for maximum priority, through the element OR 5 transfers the trigger 11 to the zero state, thereby terminating the search process for the source of the request for the maximum 0 priority. The same single signal through the prohibition element 7 enters the signal output 17 of the device, simulating a service requirement.

Upon receipt of the next request in the form of a pulse, the corresponding trigger 1 is transferred to the one state at one of the inputs. At the output of the OR 6 element, a single signal is generated that prevents the generation of the pulse Q signal "Service Requirement", translates counter 10 into the zero state, and trigger 11 is single, starting the process of finding the source of the request that has the highest priority. After the search process has been completed, a single signal appears at one of the outputs 18-5, and the service demand pulse signal is generated at the output 17 of the device.

Thus, the priority device as requested

 identification of sources with the highest priority and generates the appropriate control signals. The source identification pulse signals are combined on the element OR 20, a single signal from the output of which is fed to the input of the counter 21.

 The latter counts the source identification signals. Its capacity is set at the discretion of the device user. As soon as counter 21 is completely filled, a signal appears at its output.

0 overflow, which is fed to the input of the imager 22, at the output of which a pulse signal is produced, which zeroes the counter 28. At the second input of the element I 25 there is a high potential signal, since the trigger 23 is

5 in the zero state, which ensures the existence of this signal. Upon the occurrence of the presence conditions on the first and second inputs of the AND element 25 single signals, pulses are transmitted from the generator 8 clock pulses to the input of the delay element 26 and the counting input of the counter 28. The pulses passing through the delay element 26 are delayed by one clock cycle. that allows accurate clock output

5 shift. The clock pulses are sent to the clock inputs of registers 2. These pulses overwrite the priority codes from the first register 2 to the second, and so on.

The code from the last register 2 is rewritten to the first register 2, which constitutes a cyclical shift of priorities. At the same time, the counting of pulses from the generator of 8 clock pulses takes place, by the counter 28. After the completion of the filling of the counter 28, an overflow signal appears at its output, which is fed to the input of the imaging unit 29, at the output of which a pulse signal is output to the reset input counter 21, bringing it back to its original state, i.e. counter 21 is ready for a new priority shift cycle. If there is no overflow signal at the output of the counter 21, the clock pulses do not pass through the AND 25 element.

The remaining cycles of automatic shift of the priorities of sources according to the logic of operation are similar to those described earlier.

The device also provides for a strict temporary fixation of priorities for each source that can occur if the following conditions are met. If from the operator’s console (not shown), a pulse signal is sent to the priority blocking input 33, which switches the trigger 23 to one state, thereby prohibiting the passage of pulses from generator 8 through element 25. In the same case, the operator can perform a forced shift of priorities in registers 2. Perform a visual search for the required priority on the indicators of the group of display modules 19, it identifies the register 2, in which the priority of interest is located, and the register to which the recording should be made riteta.

When a single pulse is fed to the input 27, simultaneous formation of pulses at the outputs of the formers 30 takes place at the inputs of the corresponding delay elements 31 of the group, except for the pulse from the output of the first shaper 30. All the pulses are separated in time relative to each other by one measure, which is em at the output of the OR 32 sequence of clock pulses. After the clock pulses arrive at the clock inputs of registers 2, a shift cycle occurs, similar to the previous one. Thus, by applying pulse signals to the input 27, it is possible to achieve the setting of the required priority in the register 2 corresponding to a particular request source. The entire process of shifting the priorities is displayed on the display elements 19.

When a single signal is applied to the input 24, which triggers the trigger 23 to the zero state, the device is set to automatically shift the priorities of the sources. The service device, subject to its absence and the presence of a signal

0

"The service request begins the process of exchanging information with the selected source of the request, which in this case

sends a pulse signal on input 14 5 of the device reset input group to the zero input of the corresponding trigger 1, putting it in the zero state. At the same time, the service device generates a spike signal at the device launch input 16, through which the process of identifying the next request source having the maximum priority begins.

Claims (1)

Invention Formula 5The priority device for aut. St. No. 1137468, characterized in that, in order to extend the functionality by organizing a variable priority, both forced and automatic, it contains a group of display elements. 0 additional trigger, two additional counters, two pulse drivers, an additional AND element, an additional delay element, a group of pulse shapers, a group of delay elements, the third and fourth OR elements, with the outputs of the last group priority register connected to the additional information inputs of the first group register, each register groups are connected with additional information 0 inputs of the next group register and inputs of the same name of the group indication element, the device blocking input is connected to the single input of the additional trigger, the device blocking unlocking input is connected to the zero input of the additional trigger, the inverse output of which is connected to the first input of the additional element I, the second and third inputs of which are connected to the output of the pulse generator and the overflow output of the first. additional counter, the reset input and the counting input of which are connected respectively to the output of the first pulse shaper and the output of the third OR element, whose inputs are connected to the outputs of the AND elements of the group, the overflow output 5 of the first additional counter is connected to the input of the second pulse generator, the output of which is connected to the reset input of the second additional counter, the counting input and the overflow output of which are connected respectively to the output of the additional element And and the input of the first pulse generator, the output of the additional element And connected to the input of the additional element delay, the output of which is connected via INSTALLING OR with the output of the fourth element OR and the clock inputs of the priority group registers, the input is automatic the device’s prioritization is connected to the inputs of the group of pulse shapers, the output of the first five 1383357 56 of which is connected to the first input is even-connected through the corresponding elements of the correct element OR, the outputs of the form-delay group with the inputs of the fourth element of the group impulses, starting with the second, the ment OR.