SU1324115A1 - Device for converting binary sequence to block balance ternary code - Google Patents

Abstract

The invention relates to computing. Its use in digital information transmission systems, for example, to control these systems allows the application area to be expanded by providing the ability to operate in a wide range of frequencies. The device contains a serial-to-parallel code converter 1, a binary code switch 2, an encoding matrix 3, a switch of 4 ternary symbols, a parallel code converter to a serial one, and an Aiomoyator 6 balance code. The introduction of a clock frequency generator 7, frequency dividers 8, 9, and element 10 allows the device to operate at any desired frequency. 2 ill., 1 tab. CpU2.f

Description

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13241

The invention relates to computing and can be used in digital information transmission systems, for example, to control these systems.

The purpose of the invention is to expand the scope of application by providing the ability to work in a wide frequency range.

Figure 1 shows the functional diagram of the device; 2, time diagrams of his work.

The device contains a serial code-to-parallel converter 1, a binary code switch 2, a coding matrix 3, a switch of 4 ternary symbols, a parallel code to serial converter 5, a balance code generator 6, a clock frequency generator 7, the first 8 and second 9 frequency dividers and the And element 10. Figure 1 denotes input 11, information 12 and clock 13 outputs.

Converter 1 is made on the shift register; switches 2 and 4 are latch registers. The coding matrix can be implemented on ROM, converter 5 - on a multiplexer with a control counter. As a driver 6, an operational amplifier can be used.

The generator 7 generates a signal whose frequency is twice the frequency of the input code bits. The first divider 8 divides this frequency into two, and the second divider 9 divides the resulting frequency into three.

The signal from the output of the element And 10 is output to output 13 to control the input of the signal to the input 11. In particular, the signal from output 13 can clock the operation of a pseudo-random sequence generator (PRS) when using the device in question to control the transmission system

The operation of the device for converting a binary sequence into a block balanced trinity code will be applied to the formation of a block balanced ternary code FOMOT, which is a type of block balanced ternary code 4 GP. In this case, four-bit binary blocks correspond to blocks of three ternary symbols that take the value (+); (-); (0). View tro2

The variable block may vary depending on the value of the current digital sum at the end of the previous block. The coding transmitter is included in the coding matrix 3.

The FOMOT code translator is shown in the table.

As can be seen from the table, the main difficulty in converting is the synchronous generation of four bits of the binary sequence over three clock intervals of the ternary signal. The task is solved by using a generator 7 with a doubled clock frequency, which generates six shift pulses in three clock cycles of the ternary signal (FIG. 2, a). To eliminate two unnecessary shift pulses, an And 10 element and frequency dividers 8 and 9 are used, which form the two clock interval (figure 2 b, g, d).

As a result, the signal to input 11 is applied at a double frequency shift with stops for two clock intervals (Fig. 2, e), i.e. four bits of the binary sequence for every three clock cycles of the ternary signal,

From the input 11, a serial binary code is fed to the converter 1 of the sequential code into a parallel one. Four-bit blocks (FIG. 2, g) are fixed on the 2 binary symbol switch by block synchronization pulses from the direct output of the divider 9 (FIG. 2, c) at intervals of input signal stops. The fixing time is three clock intervals of the ternary signal. These binary blocks (Figures 2 and 2) are fed to the input of the coding matrix 3, in which the transformation algorithm defined by the table is written.

The parallel ternary blocks (figure 2, k) resulting at the output of the coding matrix 3 are gated in the switch of 4 ternary symbols by block synchronization pulses to eliminate the effect of the delay time converted in the coding matrix 3, the parallel ternary blocks (figure 2, l) arrive the input of the parallel-code-to-serial converter 5, and from its outputs ((ig.2, m, n), negative and positive polarity pulses arrive at the inputs of the imaging unit 6, at the output of which threefold mixed pulses are formed313

first code of the required amplitude supplied to the output 12 (figure 2, p).

Thus, the device is capable of operating at any frequency of a given range.

Claims (1)

Invention Formula A device for converting a binary sequence into a block balanced ternary code containing a serial to parallel converter whose information input is an input of the device, the outputs are connected to the information inputs of a binary character switch, the outputs of which are connected to the information inputs of the coding matrix, the outputs of the coding matrix are connected to the information inputs of the switch of the binary code ternary symbols whose outputs are connected to the information inputs of the steam converter -parallel-to-serial, you are a passages which are connected to the balanced input of the code output - ++ - + o + -o + 00 -o + ++ ++ + o + + oo ++ 0 + 0 + - + 1154 which is informational on the device's course, the clock inputs of the switches of binary and ternary symbols are combined, in order to expand the field of application of the device due to the possibility of operating in a wide frequency range, a frequency divider, the AND element and the clock generator are introduced into the device frequency, the output of which is connected to the first input of the element I and the input of the first frequency divider, the output of which is connected to the clock input of the converter n) of the allelic code in the coherent and input the second frequency divider, the direct output of which is connected to the combined clock inputs of binary and ternary symbol switches and the clock input of the coding matrix, the inverse output of the second frequency divider is connected to the second input of the And element, the output of which is connected to the clock input of the serial to parallel converter and is the clock output of the device. Compiled by O. Revinsky L. Veselovska Editor Tehred L. Oliynyk Korrekrr I. Korol Order 2973/57 Circulation 901 Subscription VNIIL of the USSR State Committee for inventions and discoveries 113035, Moscow, F-: 35, Raushsk nab., 4/5 Manufacturing and printing company, Uzhgorod, st. Project, 4 Extend the table