SU1499487A1 - Majority element - Google Patents

Abstract

The invention relates to the field of pulse engineering and discrete automation and can be used to build devices for processing discrete information. The purpose of the invention is the extension of functionality due to the implementation of the threshold function "5 or more out of 9". Expansion of functionality is provided by using 16-channel switches, the outputs of which are connected to the inputs of the AND element, and the inputs are connected to the outputs of the four-input And, OR elements and two threshold elements "3 or more from 4" and "2 or more from 4", whose inputs merged. The inputs of these elements and the address inputs of the switches are supplied with control and information input signals. 2 hp f-ly, 3 ill., 1 tab.

Description

The invention relates to automation and computing and can be used to build various devices for processing discrete information.

The aim of the invention is to enhance the functionality by implementing a threshold function of 5 or more of 9. In FIG. Figure 1 shows the major element structure diagram; in fig. 2 is a block diagram of a threshold element 3 or more of FIG. 3 is a block diagram of a threshold element 2 or more of 4.

The majority element contains the first 1 and second 2 switches, the AND 3 logical element, the inverter 4, the first 5 and second 6 OR elements and the threshold element 7, the first 8, second 9 and third 10 inputs of the majority element are connected to the first, second and the third address inputs of switches 1 and 2, the outputs of which are connected to the inputs of which are connected to the inputs of the first element SH 5, the output of which is the output 11 of the majority element, the inverse input of the construction of the first switch 1 connected to the input 12 of the fourth argument This majority element and the input of the inverter 4, the output of which is connected to the inverse strobe input of the second switch 2, the fifth 13, the sixth 14 and the seventh 15 input ar

4 00

of the majority element are connected to the first, second and third inputs of the AND 3 element, threshold element 7 and the second element OR 6, the first information input of the first switch 1 is connected to the bus 16 of the zero logical power1, the output of the And 3 element is connected to the second, third and fifth information inputs of the first switch 1 and the first information input of the second switch 2, the output of the threshold element 7 is connected to the fourth, sixth and seventh information inputs of the first switch 1 and the second, third and fifth information these inputs of the second switch 2, the threshold element 7 is implemented that implements the function Z.or more of 4, and the additional threshold element 17 implements the function 2 or more of 4, the first, second and third inputs of this element are connected respectively to the first, second and third inputs of the threshold element 7, the fourth input of which is the eighth input 18 of the argument of the majority element and connected to the fourth inputs of the FROM element, the second element OR 6 and the additional threshold element 17, the output of the AND 3 element is also connected to the ninth info The primary input of the first switch 1, the output of the threshold element 7 is connected to the tenth, eleventh and thirteenth information inputs of the first switch 1 and the ninth information input of the second switch 2, the output of the additional threshold element 17 is connected to the eighth, twelfth, fourteenth and fifteenth information the inputs of the first switch 1 and the twisted, sixth, seventh, tenth, eleventh and thirteenth

45

or more of 4. This is confirmed by its truth table (table)

information inputs of the second switch 2, and the output of the second element OR 6 is connected to the sixteenth information input of the first switch 1 and the eighth, twelfth, Threshold element 2 or more of the fourteenth and fifteenth information- 50 4 works as follows (Fig 3).

Upon admission to the bus variables arguments. it is output by 24-step inputs of the second switch 2, the sixteenth information and fourth address inputs of which are connected respectively to the bus 19 of a single logical signal and the ninth input 20 of the argument of the majority element, which is connected to the fourth address input of the first switch 1.

optimizes the logical function

-2 + XjX

Xjx

+ XjXg +, +

55

XeXg +

Xyxg

the corresponding threshold function is 2 or more of 4. This is indicated by its truth table (table).

0

five

0

five

0

five

0

Threshold element 3 or more of 4 (FIGO 2) contains a multiplexer 21 1 of 8 with three address inputs connected to the fifth 13, sixth 14 and seventh 15 inputs of the device arguments. And output 22. Its first, second, third and n The information inputs are connected to the bus 16 of the logical zero of the device, the fourth, sixth and seventh information inputs are from the eighth input of the 18th argument, and the eighth information input is connected to the bus 19 of the logical unit.

Threshold element 2 or more than 4 (FIG. 3) contains a multiplexer 23 1 of B with three address inputs connected to the fifth 13, sixth 14 and seventh 15 inputs of the device arguments, and output 24. Its first information input is connected to bus 16 zero, second, third, and fifth informational inputs — with the eighth input, 18 arguments; and fourth, sixth, seventh, and eighth information inputs — with a bus, 19 logical units.

The majority element works as follows.

For the implementation of the majority function of 5 or more, from 9 to the tires 8-10, 20, 12-15, 18, input inputs are supplied.

a logical threshold function of 5 or more of 9 is implemented.

The threshold element 3 or more of 4 works as follows (figure 2).

When entering tires arguments variables. it at output 22 implements a logical function

f. X, +, + +

The arguments (arguments) at output 11 are majority

.Xg +

five

,

corresponding threshold function 3

or more of 4. This is confirmed by its truth table (table)

 The threshold element 2 or more of 0 4 works as follows (Fig „3).

Upon admission to the tire variables. he is out

optimizes the logical function

-2 + XjX

Xjx

+ XjXg +, +

XeXg +

Xyxg

the corresponding threshold function is 2 or more of 4. This is indicated by its truth table (table).

51

Using the proposed device (Fig. 1), it is also possible to implement major functions of 4 or more of 7, 3 or more of 5 and 2 or more of 3. They are provided by submitting to two, four or six tires 2-5, 7, respectively. and 16-19 constants 1 or O (constant single or zero potentials) instead of variables X (according to the corresponding truth tables),

Thus, it provides the extension of its functionality and the expansion of its application area.

room

Feliner

24

Claims (3)

1. The majority element containing the first and second switches, the AND logical unit, the inverter, the first and second OR elements and the pore element, the first, second and third inputs of the arguments of the majority element are connected to the first, second and third address inputs of the switches, respectively. which are connected to the inputs of the first OR element, the output of which is the output of the majority element, the inverse gate input of the first switch is connected to the input of the fourth argument of the majority element and the input An ora whose output is connected to the inverse gate input of the second switch, the fifth, sixth and seventh inputs of the argument of the majority element are connected to the first. the second and third inputs of the AND element, the threshold element and the second element OR, the first information input of the first switch is connected to the zero logic signal bus, the output of the AND element is connected to the second, third and fifth information inputs of the first switch and the first information input of the second comm. the output of the threshold element is connected to the fourth, sixth and seventh information inputs of the first switch and the second, third and fifth information inputs of the second switch, characterized in that, in order to extend the functionality by implementing the threshold function 5 and more of 9, the first and second switches are sixteen-channel, the threshold element is implemented to implement function 3 or more of 4, and an additional A log element that implements the function 2 or more of 4 first, second and third inputs of which are connected respectively to the first, second and third inputs of the threshold element, the fourth input of which is the eighth input of the argument of the majority element and connected to the fourth inputs of the AND element, the second OR element and the additional threshold element, the output of the AND element is connected to the ninth information input of the first switch, the output of the threshold element is connected to the tenth, eleventh and thirteenth information the inputs of the first switch, and the ninth information input of the second switch, the output of the additional threshold element is connected to the eighth, twelve, fourteenth and the fifteenth information inputs of the first switch and the fourth, sixth, seventh, tenth, eleventh and thirteenth information inputs of the second switch, and the output of the second element OR is connected to the sixteenth information input of the first switch and the eighth, twelfth, fourteenth and fifteenth fifteenth information inputs of the second switch, The sixteenth information and fourth address inputs of which are connected respectively to the bus of a single logical signal and the ninth input of the argument of the majority element. which is connected to the fourth address input of the first switch. 2o The element according to claim 1, of which is that the threshold element 3 or more of 4 is performed on the switch eight channels on one, the address inputs of which are connected respectively to the fifth, sixth and the seventh inputs of the arguments of the majority element, the first, second, third and fifth information inputs are connected to the logical zero bus, the fourth, sixth and seventh information inputs are connected to the eighth input of the argument of the majority element, and the eighth information input is connected to the bus logical one. 3. Element according to claim 2, characterized in that threshold element 2 or more of 4 has eight channels per switch on the switch, whose address inputs are connected to the fifth, sixth and seventh inputs of the majority element, respectively, the first information input is connected to bus logical zero, the second, third and fifth information inputs are connected to the eighth input of the argument of the majority element, and the fourth, sixth, seventh and eighth information inputs are connected to the bus of the logical unit. Editor And, Shulla F (/. 2 Compiled by O. Skvortsov Tehred M. Didyk Order 4707/55 Circulation 884 VNIIPI State Committee for Inventions and Discoveries at the State Committee on Science and Technology of the USSR 113035, Moscow, Zh-35, Raushsk nab.,. 4/5 11 .ffSta) Fig.z Proofreader M. Maksnmishinets Subscription