SU1531210A1 - Majority element "4or more out of 7" - Google Patents

Abstract

The invention relates to automation and computing and can be used to build various devices for processing discrete information. The purpose of the invention is to increase reliability by using simpler switches with a "1 of 4" structure. The majority element contains three switches "1 out of 4", seven variable setting inputs, element 3 AND, majority element "2 or more out of 3", two elements 3 OR, element 2 OR, element EXCLUSIVE OR with inverse output, element 2I-NO , bus zero and single logic signals. 1 il.

Description

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(21) 4431294 / 24-21

(22) 05.30.88

(46) 12/23/89. Bksh. 47

(72) V.Sh.Arutiun and A.K.Arakel (53) 621.3.019.35 (088.8) (56) Abugov Yu.O., Didenko K.I., Zagariy G.I. and others. Microelectronic devices of program and logical control. - M .: Mashinostroenie, 1979, p. 41, Fig. 216.

USSR Author's Certificate No. 1448406, cl. H 03 K 29/33, 16.11.87 (54) MAJORITY ELEMENT 4 OR MORE OF 7 (57) The invention relates to automation and computer technology and can be used to build various devices for processing discrete information. The purpose of the invention is to increase reliability by using simpler switches with a structure of 1 out of 4. The major element contains three switches 1 of 4, seven variable assignment inputs, element 3 AND, majority element 2 or more of 3, two elements 3 OR, element 2 ШШ, element EXCLUSIVE ШШ with an inverse output, element 2 И-НЭ, are inherent in zero and single logical signals. 1 il.

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The invention relates to automation and computing and can be used to build various devices for processing discrete information.

The purpose of the invention is to increase reliability.

The drawing shows a block diagram of the majority element.

 The majority element contains the first 1, second 2 and third 3 switches 1 of 4, seven inputs 4-10 of the variables X, - X, the ZIP element, the majority element 12c

logic 2 or more of 3, the first element 3 OR 13, the second element 3 И1Ш 14, the element 2 ШШ 15, the element EXCLUSIVE OR 16 with the inverse output, the element 2 IS-NOT 17, the bus 18 zero logic signal, the bus 19 single signal and output of the 20 major element.

The first 4 and second 5 inputs are connected respectively to the first and second address inputs of the first 1 and second 2 switches, the inputs of element 3 and 11 are connected to the fifth and 8, there are 9 and seven M1M 10 input inputs

the information inputs of the first switch 1 and the first information input of the second switch 2, the inputs of the majority element or more of IE 3 12 are connected to the fifth 8, six 9 and seven 10 inputs are variable, and the output has a quarter information input (Я4 of the first switch 1 and with the second and third information inputs of the second switch 2, the inputs of element 3 OR 13 are connected to the fifth 8, sixth 9 and seventh 10 inputs of the variables, and the output is connected to the fourth input of the second switch 2 bus 18 of zero logical potential connected to the first info The first input of the first switch is 1. The inputs of element 3 OR 14 are connected to the outputs of the first 1 and second 2 switches, and the output is the output of the 20 major element. The inputs of elements 2 of the HSR 15 are EXCLUSIVE OR 16 and 2 AND-NOT 17 connected to the third 6th and fourth 7th input of o1 reversal, and the output h, respectively, to the gating inputs of the first 1, second 2 and third 3 switches; the address inputs of the third terminal 3 and 3 are connected respectively to the first 4 and

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the second 5 inputs of variables, its first information input - with the output of the majority element 12 2 or more out of 3, the second and third information inputs - with the output of element 3 OR 13, the fourth information input - with the bus 19 of a single logical signal, and the output - with the network input element 3 OR 14.

The majority element works in the following way.

For the implementation of the majority function of 4 or more of 7, input variables X - X are supplied to inputs 4-10. When there are four or more units in the input code combinations, a single logic signal is generated at the output of the 20th major element. For all other codewords, there is a zero logic signal at output 20.

The implementation of a majority function device of 3 or more out of 5 is carried out when two of the variable inputs are given zero logic signals. A majority function of 2 or more of the 3 is realized when four of the variable inputs are applied to zero logic signals.

Claims (1)

Invention Formula The major element 4 or more of 7, containing the first and second pcrft switches with strobe inputs, seven variable assignment inputs, the first and second of which are connected respectively to the first and second address inputs of the first and second switches, element 3 AND, inputs which are connected to the fifth, sixth and seventh inputs of variables, and the output is connected to the second and third information inputs of the first switchboard and the primary information input DSYa4 of the second switchboard, the majority element 2 or more of 3, whose inputs are connected to the fifth , Shestm and seventh input variables, output - with the fourth information input of the first switch and with the second and third information inputs of the second switch, element 3 SHS, which is connected to the fifth, sixth and sed1 "1st inputs belt, and the output - with the fourth information input of the second switch, the zero bus signal, which is connected to the first information input of the first switch, the bus of a single logical signal and the first OR element, the first and second inputs of which are connected to the outputs of the first and second switches, and the output is the output of the majority element, increase the reliability, the first and second switches are made with the structure of 1 of 4, the element additionally contains the third switch 1 of 4, the second element OR, the element EXCEPTING OR with the inverse output and the element 2 AND-NOT, and the first element OR with holds the third entrance. 12104 the inputs of the second element OR, EXCLUSIVE CHAKHTSEE OR and 2 AND-NOT are connected to the third and fourth inputs of the variables, and the outputs respectively with the gate inputs of the first, second and third switches, the address inputs of the third switch are connected respectively to the first and .Q second inputs of the variables, its first information input is with major element 2 or more 3, the second and third information inputs - with the output of the first element 3 OR, the fourth information input - with the bus of a single logic signal, and the output - with the third input of the first element OR.