SU1448406A1 - Majority element - Google Patents

Abstract

The invention relates to a pulse technique and discrete automation and can be used to build various devices for processing discrete information. The purpose of the invention is to expand the functional capabilities and the field of application of the device by implementing the majority function of 4 out of more than 7. Additional functionality is provided with AND 12, 2 or more of 3 13 and OR 14, whose inputs are combined and to which The input signals go out, and the outputs are connected to the inputs of switches 1 and 2, the outputs of which are connected to the inputs of the element OR B, from the output of which the required function is removed. 1 il. W with Sl & xsffJ

Description

The invention relates to automation and computing and can be used to build various devices for processing discrete information.

The purpose of the invention is to expand the functionality and application area of the device by implementing a majoritarian function of 4 or more out of 7,

The drawing shows a structural diagram of the proposed major element.

The majority element contains the first 1 and second 2 switches 1 of 8, the same address address inputs (A1 - A3) of which are interconnected and connected respectively to the first 3 (X), second 4 (Xj) and third 5 (Xj) inputs of the task variables, the fourth 6 (X) variable setting input, inverter 7, logical element OR 8 output 9 of the majority element, bus 10 of a single logical signal, fifth (X |.) input 1 1 variables and logical elements ZI 12, majority element 2 or more from 3 13, element ZILI 14, sixth 15 (X (,) and seventh 16 (X) inputs for setting variables The first information input of the first switch j is connected to the zero logic signal bus, the inverse gate input of the first switch 1 is connected to the fourth input 6 of the variable assignments, the input of the inverter 7 is connected to the inverse gate of the first switch 1, and the output is connected to the inverse input of the groove the second switch 2, the inputs of the logical element OR 8 are connected to the outputs of the first 1 and second 2 switches, and the output is the output 9 of the majority element. The inputs of the ZI element 12 are combined with the corresponding inputs of the majority element 2 or more 3 13 and the ZILI element 14 and are connected to the fifth P, sixth i 5 and seventh 16 task inputs

variables, the output of the element ZI 12 soe-JQ of which is connected to the inverse input

dinene with the second, third, fifth information inputs of the first switch 1 and the first information input of the second switch 2, the output of the primary element 2 or more of 3 13 is connected to the fourth, sixth, seventh information inputs of the first switch 1 and the second, third them, fifth information inputs

gating the first switch and the output with the inverted input of the second switch of the second switch, the logical element OR, whose inputs are connected to the outputs of the first and second switches, and the output is the output of the majority element, the bus of a single logical signal that is connected to the eighth informational

0

0

five

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the second switch 2, the output of the ZILI element 14 is the eighth information input of the first switch and the fourth, sixth, seventh information inputs of the second switch, and the eighth information input of the second switch 2 is connected to the bus 10 of a single logical signal.

The majority element works as follows.

For the implementation of the majority function of 4 or more from 7, input variables (arguments) X, - ic are supplied to buses 3-6, P, 15 and 16. In this case, at the output 9 of the majority element, a logical threshold function of 4 or more of 7 is implemented.

Using the proposed device, it is also possible to implement the majority functions of 3 or more of 5 and 2 or more. 3. The implementation of the proposed function of the majority functions of 3 or more of 5 and 2 or more of 3 is provided by feeding to two or four tires 3-6, 11 , 15 and 16 constants 1 or O (constant unit or zero-potentials) instead of variables X.

This provides enhanced functionality.

and, thereby, expanding the scope of the majority element.

Claims (1)

Invention Formula The majority element containing the first and second switches of 8 of the same address inputs of which are interconnected and connected respectively to the first, second and third inputs of the variable variables, the first information input of the first switch is connected to the zero logical signal bus, the inverse gate input of the first switch is connected to the fourth input variable assignment, inverter, input to gating of the first switch, and the output with the inverse input of the second switch of the second switch, the logical element OR, whose inputs are connected to the outputs of the first and second switches, and the output is the output of the majority element, the bus of the single logical signal which connected to the eighth information the input of the second switch, the fifth input of the variable setting, characterized in that, in order to expand the functionality and application area by implementing a logic function 4 or more of 7, the GI element, the majority element 2 or more of 3, the element ZHSH, the sixth and seventh inputs of the variables setting, the inputs of the ZI element are combined with the corresponding inputs of the majority element 2 or more of 3 and the ZIPPI element and are connected to the fifth, neck and seventh inputs of the transducer 15 448406 The output of the ZI element is connected to the second, third, fifth information inputs of the first switch and the first information input of the second switch, the output of the majority element 2 or more of 3 is connected to the fourth, sixth, seventh information inputs of the first switch and the second, third, fifth information inputs of the second switch; the output of the ZILI element is connected to the eighth information input of the first switch and to the fourth, sixth, seventh information inputs of the second switch. ten