SU1323973A1 - Device for comparing signal frequencies - Google Patents

Abstract

The invention relates to a technique for measuring the ratio of the frequencies of two signals with a counting-pulse method. The purpose of the invention is to expand the functionality and simplify the device. The device contains drivers 1 and 2, elements OR 15, 16, counters 7 and 8 pulses, elements 9 and 10 of the display, elements 3, 4, II -14, 17, frequency divider 18, element 19 and decimal counter 20, including decades 20.1 and 20.2. code 21 and 22 and a differentiating circuit 23. The introduction of the elements OR 5 and iS and the execution of counters 7 and 8 pulses with a recalculation factor of two eliminates restrictions on the synchronization of the input frequencies. 1 il. O) 00 yo SA :) with OO

Description

The invention relates to a technique for measuring the frequency ratio of signals by a counting method.

The purpose of the invention is enhanced functionality and simplification.

The drawing shows a functional diagram of the device.

The device consists of the formers 1 and 2, the first 3 and second 4 elements AND, the third 5 and fourth 6 elements OR, the first 7 and second 8 pulse counters, the elements 9 and 10 of the display, the first 11, ujecToro 12, the seventh 13 and fourth 14 AND elements, first 15 and second 16 OR elements, third AND element 17, frequency divider 18, NOT element 19, decimal counter 20 consisting of decades 20.1 and 20.2, two decoders 21 and 22, differentiating 1.epi 23 and input tires 24 and 25.

The device contains two imagers 1 and 2, the outputs of which are connected to the first inputs of the first 3 and second 4 elements I, respectively, and the inputs to the input buses 24 and 25, three counters 7, 8 and 20 pulses, the inverse outputs of counters 7 and 8 are connected to the second inputs of the first 3 and second 4 elements And, respectively, the element NOT 19, the input of which is connected to the first input of the third element And 17, the frequency divider 18, two elements 9 and 10 of the display, the first 15 and second 16 elements OR, the fourth 14, the fifth 11, sixth 12 and seventh

The 13 And elements, two decoder 21 and 22, differentiate the chain 23, the second inputs of the counters 7 and 8 are connected to the outputs of the And 3 and 4 elements, respectively, the input of the differentiating chain 23 is connected to the output of the element 19 HE and the installation input of the counter 20, which is - the unified inputs of the installation of its serially connected decades 20.1 and 20.2, the outputs of which are respectively connected to the decoders 21 and 22, and the counter input of the counter 20, which is the input of the first decade 20.1, through the third element 17 AND and the first element 15 OR connected to the outputs n Togo 11 and sixth And 12 elements, the first inputs of which are respectively connected to the first inputs of the fourth 14 and seventh 13 elements And, and the second inputs to the elements 9 and 10 of the display and to the forward outputs of the first 7 and second 8 pulse counters, respectively, This second element 16 OR is connected through a frequency divider 18 to the input of element 19 NOT, and the inputs of the second element 16 OR to the outputs of the fourth

14 and seventh 13 And elements, the first inputs of which are respectively connected to the first inputs of the second 4 and first 3 And elements, and the second inputs to the direct outputs of the second 8 and first 7 pulse counters, as well as the third 5 and fourth 6 OR elements. Counters 7 and 8 are made with a conversion factor of two, and B1) 1.od of the second element 4 AND and the output of the differentiating circuit 23 through the fourth element 6 OR, and the output of the first element 3 AND and the output of the differentiating circuit 23 through the third element 5 OR are connected with the set first inputs of the second 8 and first 7 pulse counters, respectively.

The device works as follows.

In the initial state, the counters 7, 8 and 20 are set to the zero state at the outputs.

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(counters 7 and 8 are in the zero state at direct outputs and one inverse).

The harmonic signals arriving at shaper 1 and 2 with frequencies fi and 2 are converted into regular pulse sequences with frequencies fi and fa, and let (for definiteness) pulse f2 arrive before fi.

Let f2 F. The first impulse fa, the passage through element 4 I (since at its second input there is a unit level from the inverse output of counter 8), sets counter 8 to the zero state (confirms the zero state) at the forward output and the unit to inverse. Acting on the counting input of the counter 7, it is memorized (recorded) in it.

Then comes the first impulse f |. Pro- going through element 3 I (since its second input is a single level from the inverse output of counter 7), it returns counter 7 to its original state (zero states of all the triggers that comprise it). Acting on the counting input of the counter 8, it is remembered in it.

When the pulses fi and fv alternate, the described states of the elements are repeated. At the outputs of counters 7 and 8, the state is not changed. Elements 11-14 and closed by zero levels from the direct outputs of counters 7 and 8.

When two additional pulses fv arrive, the counter 7 is filled, at its inverse output a zero level X is formed, which, entering the second input of the element 3, closes it, thereby stopping the arrival of the pulses f | The counting input of the counter 8 and the input of the installation to the zero state of the counter 7. The unit level from the output of the counter 7 is fed to the input of the indicator element 9, and the light signal f2 f |.

The sequence of pulses fv arriving at the counting input of the counter 7, does not change the single state at its output, the input to the installation of the zero state of the counter 8, also does not change the zero state at its output.

The unit level from the direct output of counter 7, arriving at the second And and 13 And elements, pa3penjaeT, the passage of pulses of higher frequency (fv) through the element 11 And, and further through the element 15 OR, and of a lower frequency (fi) through the element 13 AND and further through the element 16 OR.

The pulses from the output of element 16 OR are fed to the input of the divider 18 frequency (which divides this frequency 10 n times) and then to the first input of the element 17 I, allowing the passage through it of pulses of greater frequency Gg (from the output of element 15 OR) to the input of the decimal the counter 20, the decades 20.1 and 20.2 of which, respectively, read the fractional and integer parts of the number corresponding to the ratio fi and 9. Next, the signals are sent to the decoders 21 and 22.

If the 18 hour divider is set at a dividing factor of 10 and there are two decades of counter 20, then the frequencies fi and f2 are compared with an accuracy of tenths.

Let fi 2. The operation of the device (until the arrival of two different frequency pulses) is completely analogous to that described.

When two additional pulses fi arrive, the counter 8 is filled and at its inverse output a zero level is formed, which, entering the second input of the element 4, closes it, thereby stopping, and the arrival of the pulses fo at the counting input of the counter 7 and the installation input the zero state of the counter 8. The unit level from the direct output of the counter 8 is fed to the input of the indicator element 10, the light signal fi f2.

Subsequent pulses fi, arriving at the counting input of the counter 8 and at the input of setting the zero state of the counter 7, do not change their state.

A single level from the direct output of the counter 8, arriving at the second inputs of elements 12 and 14 AND, allows the passage of pulses of higher frequency (f |) through element 12 And further through element 15 OR, and lower frequency (f2) through element 14 And further through the element 16 OR.

The operation of the device is further similar to that described. The device is reset to the initial (initial) state at the end of the pulse at the first input of the element 17 AND coming from the frequency divider 18. The signal "O through element 19 is NOT applied to the installation inputs to the zero state of the counter 20 and translates it to the zero state. The same signal through the differentiating circuit 23 is fed through the elements 5 and 6 OR to the inputs of the installation in the zero state of the counters 7 and 8 and converts them to the initial state. The device is ready for a new frequency comparison cycle.

Simplification of the proposed device is achieved by reducing the size of the counters 7 and 8, and the expansion of functionality is due to the absence of the editor E. Kopcha Order 2962/50

Compiled by E. Minkin

Tehred I. VeresKorrektor S. Cherni

Circulation 730 Subscription

VNIIPI USSR State Committee for Inventions and Discovery

1 13035, L Oskva, Zh-35, Raushsk Nab. D. Production Polygraphic Enterprise, Uzhgorod. l Design. four

0

We will limit the synchronization of input frequencies.

Claims (1)

Invention Formula A device for comparing the frequencies of signals containing two formers, the outputs of which are respectively connected to the first inputs of the first and second elements AND Q inputs are connected to the input buses, three pulse counters, inverse outputs of the first and second of which are connected to the second inputs of the first and second elements AND, respectively, the element NOT whose input is connected to the first input of the third And, the frequency divider, as well as two display elements, the first and second elements OR, the fourth, fifth, and the seventh And elements, two decoders and a differentiating circuit, the second inputs of the first and second counters connected to the outputs of the first and second And elements, respectively , the input of the differentiating circuit is connected to the output of the element NOT and the installation input of the third pulse counter, which are the combined inputs 5 setting up its serially connected decades, the outputs of which are respectively connected to the decoders, and the counting input of the third counter, which is the input of its first decade, through the third element AND and the first element OR are connected to the outputs 0 of the fifth and the second elements And, the first inputs of which are respectively connected to the first inputs of the fourth and seventh elements And, and the second inputs to the display elements and to the direct outputs of the first and second pulse counters, respectively, 5, the output of the second element OR is connected through the frequency divider to the input of the element NOT, and the inputs of the second element OR to the outputs of the fourth and seventh elementand AND, the first inputs of which are respectively connected but to the first inputs of the second and first elements AND the second inputs are with direct outputs of the second and first pulse counters, characterized in that, in order to extend the functionality and simplify, a third one is introduced into it 5 and the fourth element OR, and the first and second counters are made with a conversion factor of two, with the output of the second element AND and the output of the differentiating circuit through the fourth element OR, and the output of the first element AND and the output of differentiating 0 circuit through the third element OR connected to the installation inputs of the second and first counters, respectively.