SU1310781A1 - Device for checking exponential processes - Google Patents

Abstract

The invention relates to computational and instrumentation technology and can be used to control exponential transients in various technological objects, such as power units. The purpose of the invention of the shadow is to increase the speed control of the established values of the exponential processes. The device for controlling exponential processes contains threshold elements 1-3, analog converter - pulse duration 4, single pulse generators 5-7, triggers 8-10, shift registers 11 and 12, adders-subtractors 13 and 14, frequency divider 15, counter 16, a group of display elements 17, elements AND 18-25, elements OR 26-30, a delay element 31, display elements 32-34, and a synchronization unit 35. The device improves the control performance of the steady-state value of the exponential process by predicting this value, as well as Determines whether this value passes a valid level. 1 hp f-ly, 3 ill. jr i SL with. 00

Description

The invention relates to computational and instrumentation technology and can be used to control exponential transients in various technological objects, such as power units.

The purpose of the invention is to increase the speed of monitoring the established values of the exponential processes.

Figure 1 shows a block diagram of a device for monitoring exponential processes; figure 2 - block diagram of the synchronization unit; FIG. 3 is a time diagram of a controlled exponential process.

A device for controlling exponential processes (Fig. 1) contains threshold elements 1-3, converter 4 analog - pulse duration, generators 5-7 single pulses, triggers 8-10, shift registers 11 and 12, adders-readers 13 and 14 , frequency divider 15, counter 16, display element group 17, And 18-25 elements, elements

ten

15

20

25

generator 40 pulses of the synchronization unit 35, since their installation inputs are acted upon by the signal O. In the initial state, at the output of the key 45, the synchronization unit 35 operates. the signal O, which, arriving at the clock input of the generators 5-7 single pulses, blocks their operation,

 The pulse generator 40 of the synchronization unit 35 forms a sequence of clock pulses of frequency f, of which the frequency divider 41 generates a sequence of pulses of frequency f / n, where n is the number of bits of the registers 11 and 12 of the shift.

From the output sequence of the frequency divider 41, the delay unit 42 per clock of the synchronization unit 35 generates a sequence of frequency pulses f / n synchronizing the moments of reading the lower (first) bit of the binary code from shift registers 1 and 12.

The pulse sequence at the output of the frequency divider 41 synchronizes the moments of reading the higher (nth) bit of the binary code OR 26-30, delay element 31, an elec tor from shift recorders 11 and 12, cops 32-34 of the display, block 35 sync Element NO 43 synchronization synchronization block 35, inputs 36-38 of the reference voltages and information input 39.

generates an inverse pulse sequence output frequency divider 41.

The synchronization unit 35 (FIG. 2) contains a pulse generator 40, a frequency divider 41, a delay element 42, a HE element 43 and 44, keys 45 and 46, outputs 47-52, which are respectively the first to sixth outputs of the synchronization unit 35 .

The device for controlling exponential processes works as follows.

In the initial state, key 46 of the synchronization unit 35 connects the Element element NO 44, on which signal 1 operates, to the installation inputs of the frequency divider 15 and the counter 16, to the control inputs of the shift registers 1 and 12 and through the elements of the Q pulses. At the output of key 46, delays 28 and 29 are connected to the reset inputs of triggers 8-10.

Under the action of the signal I, the triggers 8-10, the shift registers 11 and 12, the frequency divider 15 and the counter 16 are reset to the initial zero state. The shift registers 11 and 12 are set to the zero state under the action of clock pulses.

signal O.

An information signal 39 of the device is supplied with an analogue signal Ll (t) of the controlled transient, j varying exponentially and, and (1st 2) where and is the unknown steady-state value of the exponential transient (Fig. 3); oi - expo indicator

generator 40 pulses of block 35 synchronization, as they are installed. The O. signal acts in the active inputs. the signal O, which, arriving at the clock input of the generators 5-7 single pulses, blocks their operation,

 The pulse generator 40 of the synchronization unit 35 forms a sequence of clock pulses of frequency f, of which the frequency divider 41 generates a sequence of pulses of frequency f / n, where n is the number of bits of the registers 11 and 12 of the shift.

From the output sequence of the frequency divider 41, the delay unit 42 per clock of the synchronization unit 35 generates a sequence of frequency pulses f / n synchronizing the moments of reading the lower (first) bit of the binary code from shift registers 1 and 12.

The pulse sequence at the output of the frequency divider 41 synchronizes the moments of reading the higher (nth) bit of the binary code from the recorders 11 and 12 of the shift, the element is NOT 43 of the synchronization unit 35

generates an inverse pulse sequence output frequency divider 41.

In the transient control mode, described by an exponential function, the inputs 36–38 of the device are connected to the outputs of the reference voltage sources with the reference voltage levels U, U2 and Uj, respectively, and U U: U U and. U2 - U Uj - U (Fig. 3), the values of U, U and Uj are in the allowable range of change

45 process Ll (t),

The key 45 of the synchronization unit 35 connects the 4-frequency divider output of the synchronization unit 35 to the clock inputs of 5-7 single generators

Q pulses. At the output of the key 46, a signal O.

An information signal 39 of the device is supplied with an analogue signal Ll (t) of the controlled transient, j varying exponentially and, and (1st 2) where and is the unknown steady-state value of the exponential transient (Fig. 3); oi - expo indicator 3131

a potential function whose value is unknown during control; t is the time from the beginning of the transition process.

The device solves the control problem, without waiting for the end of the transition process, determines whether the value of the steady state passes to the zero level;

In the initial state, zero signals act at the output of the 1-3 elements. As soon as the input voltage acting on the device information input 39 reaches the reference voltage level U, a single signal is generated at the output of the threshold element 1, which starts the generator 5 of single pulses. A single pulse generated by the generator of 5 single pulses from the pulse sequence of the output of the frequency divider 41 of the synchronization unit 35 sets the trigger 8 to one and through the OR 27 element starts the converter 4 analogue - the pulse duration. A single signal of the direct output of the trigger 8 triggers the indication element 32, removes the blocking element AND 18 and after the delay time of the elements 31, equal to the pulse duration, removes the blocking element AND 22, through which the sequence of the frequency divider 15 begins to arrive pulse output divider 41 frequency block 35 synchronization.

At the output of the converter 4 analogue — the pulse duration, a pulse is formed, the duration of which is progressively distributed to the analog signal acting on the information input 39 of the device.

The sequence of output pulses of the delay element 42 of the synchronization unit 35 goes through the element AND 18 to the first input of the subtractor 14 and through the elements 21 and OR 26 to the first input of the block 13.

The single signal of the direct output of the trigger 8 through the elements AND 24 and OR 30 goes to the control inputs of the adders-subtractors 13 and 14, sets the adder-subtractor 13 to summing mode, and the adder-subtractor 14 to subtracting mode.

At the first input of the adder-subtractor 13 acts through the elements

14

And 18, 21 and OR 26 a sequence of pulses of a synchronization unit 35, the number of which is proportional to the duration of the output pulse of the converter 4 analogue - the duration of the pulse.

Using the adder-subtractor 13. operating in the summation mode, in the shift register 11 is formed

binary code whose value

equal to the number of pulses received at the output of the element 21, controlled by the output pulse of the converter 1; the analog 4 is the duration

momentum.

The first impulse of the sequence acting on the first input of the adder-subtractor 13, on its first directional waveform, forms an impulse which, under

the action of the clock pulses of the pulse generator 40 of the synchronization unit 35 is written to the shift register 11 and after the n clock cycles it is read to the second input of the sub-meter-read function

bodies 13 at the time when the first pulse of the sequence acts on its first input. At the first output of the adder-subtractor 13, a serial binary code 00 ... 010 is formed, which, starting with the low-order bit, is written to the shift register 11 and after the n cycles, the second input of the subtractor 13 is shifted again. If the first input of the adder is Since the subtractor 13 received a bundle of K pulses, then after the K p clock cycles in the shift register 11, a binary code is generated, the value of which is K.

Simultaneously with the help of

adder 14, operating in the subtraction mode, in the shift register 12 is formed an additional

the binary code of value 2 is K. The first pulse of the sequence acting at the output of the element 18 is subtracted by the adder-subtractor 14 of their initial zero register code

12 shift shifted under the action of the clock pulses of the generator 40 pulses of the block 35 synchronization. At the output of the adder-subtractor 14, additional binary code 11. ,, 111 of the value 2-I is generated in steps of 2, which, under the action of the clock pulses of the generator 40 of the pulses of the synchronization unit 35, is written, starting with the least significant bit,

5 1h:

shift register I2 and after n clock cycles again is shifted to the second input of subtractor 14.

The inverse sequence of pulses of the divider 41 of the frequency of the synchronization unit 35, acting at the output of the HE element 43, blocks the AND 24 element in n cycles, the zero signal of which through the OR 30 element blocks the loan signal from the nth digit through the OR subtractor 14.

Further, the device operates similarly until the end of the pulse at the output of the converter 4 analogue — the pulse duration. The zero signal at the output of the converter 4 analogue - the pulse duration blocks the element And 21, and a zero signal is set at the first input of the adder-subtractor 13.

A binary code proportional to the analog signal acting on the information input 39 of the device is dynamically memorized by circulating, under the action of the clock pulses of the pulse generator 40, the synchronization unit 35 from the output of the shift register 11 through the adder-subtractor 13 to the information input of the shift register 11,

At this time, in the shift register 12, an additional binary code of the value 2 - i continues to be formed, where i is the number of pulses acting at the output of the AND 18 element, equal to the number of the calculation cycle, if one cycle takes n cycles,

Subsequently, the device operates similarly until the pulse appears at the output of frequency divider 15, the division ratio of which is chosen so that the follow-on period of the output pulses of frequency divider 15 is longer than the output pulse duration of converter 4 analog — the pulse duration for the maximum possible voltage level information input device 39.

Therefore, a pulse at the output of frequency divide 15 is formed after the end of the pulse at the output of the converter 4 analogue - the pulse duration. The output pulse of the frequency 15 frequency re-starts the transducer 4 analog - the pulse duration, which forms a pulse with a duration proportional to 16

current value of the voltage on the information input 39 of the device. At the output of the element 21, a burst of pulses is formed, the number

which is proportional to the pulse duration of the converter 4 analogue - the pulse duration. A bundle of pulses from the output of the element 21 through the element ШШ 26 enters the first

input of the subtractor 13, to the second input of which, under the action of the clock pulses of the generator 40 of the pulses of the synchronization unit 35, shifts from the output of the shift register 11 a serial binary code, the value of which is proportional to the voltage level on the information input 39, which was in effect during the first interrogation cycle - pulse duration.

For each pulse of the packet, the adder-subtractor 13 increases the binary code of the shift register 11 by one LSB and the successive binary result code is written to the shift register 11 for the duration of the n cycles. Thus, in the shift register 1, a binary code is accumulated, the value of which is proportional to the integral of the analog signal of the increasing exponential function acting on the information input 39 of the device since the threshold element 1 triggers,

In the shift register 12, the value is accumulated in the additional code, is proportional to the time from the moment the threshold element 1 is triggered,

Subsequently, the device operates similarly until threshold element 2 is triggered when the voltage at information input 39 of the device reaches the reference voltage level Uj. In this case, a single signal is generated at the output of the threshold element 2. It triggers a generator of 6 single pulses, the output impulse of which sets the trigger 9 into a single state. The trigger 9 in the single state blocks the AND 24 element with the inverse-output signal and leads to the trigger signal from the direct output.

the element And 19 and the element 33 of the display,

Single output signal element And 19 nepeKJD04aeT adder-subtractor

713

13 into the subtraction mode, and the adder-subtractor 14 into the summing mode. By the time the threshold element 2 is triggered in the shift register 11, a binary code is generated that is proportional to the integral of the input voltage acting on the information input of the device acting on the information input 3 on the time interval where t. and t are the response times of the threshold elements 1 and 2, respectively,

In the shift register 12, an additional code 2 - S is formed, where S is the number of computation cycles in the time interval t t The value of S is proportional to the time interval tj t - S n / f, where n is the number of bits in registers 11 and 12 of the shift; f is the frequency of the clock pulses of the generator 40 pulses of the synchronization unit 35.

After the threshold element 2 is triggered, the adder-subtractor 13 subtracts from the binary code of the shift register register 11 the pulses generated by the output of the AND 21 element under the action of the output pulses of the analog-pulse width converter 4, which is polled through the OR element 27 by a sequence of frequency divider 15 pulses

For each pulse acting on the first input, the adder-subtractor 13 reduces the binary code shifted from the output of the shift register 11 per unit of the least significant bit during n clock cycles and the result of the subtraction is again recorded in the shift register 11 under the action of the clock pulses of the generator 40 pulse block 35 synchronization.

At this time, for each pulse acting on the output of the AND 18 element, the adder-subtractor 14 increases the additional binary code shifted from the output of the shift register 12 by one least significant bit during the n clock cycles and the result of the summation is shifted again into the shift register 12 under the action clock pulses of the generator 40 pulses of the synchronization unit 35.

The inverse sequence of pulses of the frequency divider 41 of the synchronization unit 35, acting at the output of the element NO 43, blocks the element E 19 in n-ticks and zero sig 18

The cash of which is blocked in the accumulator 13, the loan signal from the nth digit, and in the subtractor 14, the transfer signal from the nth digit

bit

In the following, the device operates similarly as long as the input level of the reference voltage Uj. In this case, the threshold element 3 triggers, the output signal of which triggers the generator of 7 single pulses. A single pulse generator 7 single pulses sets the trigger 10 in a single

the state and through the element OR 28 sets in O triggers 8 and 9. By the time the threshold element 3 is triggered in the shift register 11, an additional code of the difference of the integrals from the increasing exponential function is formed on the time intervals t, - tj and t2 t, where t J is the moment the response time of the threshold element 3. The difference of the integrals in the shift register 11 is formed in the additional code, since at the levels of the reference voltages Uj - U2 and - and the integral of the increasing exponential function

on the interval t - t, it is always greater than the integral on the interval t 11 (FIG. 3).

In shift register 12, a binary is generated by time tj

code proportional to the difference in time intervals (tj- t) - (tj - ti) (Sj - Si) n / f, where S is the number of calculation cycles in the time interval t ,, - t2- The binary code in register 12 is shifted to time t, is positive, since at the levels of the reference voltages Uj - U2 U j - U for an increasing exponential function is always (.tj) (zi

Triggers 8 and 9, after setting them to the zero state, block elements AND 24 and 19, respectively.

The zero signal of the direct output of the trigger 8 through the delay element 31 blocks the element And 22, stopping the arrival of pulses at the input of the frequency divider 15. Element and 18 also

enters the blocking mode under the action of the zero signal of the direct trigger output 8. The zero signal of the element output And 18 blocks the element. And 21.

91

A single signal of the direct output of the trigger 10 triggers the display element 34, removes the blocking of the AND 23 and 25 elements, and through the OR 30 element switches the adder-subtractor 13 into the summation mode.

The adder 14 stops the computations with zero signals arriving at its first input from the output of the element 18. Therefore, the binary code of the shift register 12 generated by the time t ,, is dynamically memorized by circulating under the action of the clock pulses of the pulse generator 40

the synchronization block 35 of the binary code from the output of the shift register 12 through the adder-subtractor 14 to the information input of the shift register 12. The binary code shifted from the output of the shift register 12 comes from the output of the subtractor of the subtractor) 4 through the elements 23 and ШШ 26 to the first input adder 13, to the second input of which from the output of shift register 11 shifts the additional code of the difference of the integrals on time intervals tj - tj, and t2 t, Adder-13 reads the sum of consecutive binary codes, and the result vaets starting from the LSBs in the shift register 11 under the influence of the clock pulse generator 40 synchronizing unit 35. At this time, the state of the counter 16 is changed by one, since its information input during the p-cycles receives through the AND 25 element one pulse of the sequence acting at the output of the delay element 42 of the synchronization unit 35.

Subsequently, the device operates similarly until the second output of the adder-subtractor 13 does not show the transfer signal from the n-th bit, which opens the element AND 20, the pulse of the output sequence of the frequency divider 41 of the synchronization unit 35 through the elements AND 20 and OR 29 sets trigger 10 to the zero state, at which AND 23 and 25 are blocked.

The blocking of the element And 25 stops the counting process in decimal counter 16, in which by setting the number proportional to the value of Uni to the set value of age 0781

ten

melting exponential process, although the transition process has not yet been completed (Fig. 3).

With the help of a group of display elements 17, even before the transition process is completed, the information input 39 of the device provides the control operator with a predictable value U at a steady-state value of the exponential process.

The proposed device allows controlling the predicted steady-state value of parameters of various technological objects.

during the transitional exponential process in the permissible range of change, without waiting for it to end with the achievement of alarm values.

I

The capacity of the counter 16 is selected

equal to the maximum permissible value and the steady-state value of the parameters U (t) of the object (electrical,

thermal, etc.), which, under operating conditions, varies exponentially, for example due to load buildup or disturbance.

In the case of danger of a steady-state value of a parameter, an object equal to or exceeding the maximum permissible value, the counter 16 overflows during the end of the transition process. To indicate an overflow of the counter 16, one of the elements 17 may be implemented as an indicator providing an alarm or automatically turning on the security system of the object.

Claims (1)

Invention Formula one . A device for counteracting / l of exponential processes containing an analogue converter — pulse duration, first shift register, first adder-subtractor, first and the second trigger, the first and second elements of the IPD, the first, second, third and fourth elenty And, a group of display elements and a synchronization unit, the second output of which is connected with the synchronization input of the first shift register, the direct outputs of the first and second triggers are connected respectively to the first inputs of the first and second elements And, the second inputs 1113 which are connected respectively to the third and fourth outputs of the synchronization unit, the first and second outputs of the adder-subtractor are connected respectively to the information input of the first shift register and the first input of the third element And, the first information input of the adder-subtractor is connected to the output of the first element OR, information input analogue converter - the pulse duration is an informational INPUT of the device, which is distinguished from the fact that, in order to increase the speed of monitoring the established values exponential processes of the device; the first, second and third generators of single pulses, the second shift register, the second adder-subtractor, frequency divider, counter, third trigger, third, fourth and fifth elements OR, fifth, sixth, seventh and eighth are entered into it And elements, the delay element, the first, second and third display elements, the first, second and third threshold elements, the inputs of which are connected to the information input of the device, and the outputs of the first, second and third threshold elements are connected respectively. control inputs of the first, second and third single pulse pulsers, the clock inputs of which are connected to the first output of the synchronization unit, and the outputs of the first, second, and third generators of single pulses are connected to the installation inputs of the first, second, and third triggers, respectively; connected to the inputs of the first, second and third display elements, the input of the third display element is connected to the second input of the fifth OR element, to the first input of the sixth And element, and to the first th input of the eighth element And, the second input of which is connected to the third output of the synchronization unit, the fifth output of which is connected to the second input of the fifth element And and the second input of the third element And, the output connected to the second input of the fourth element OR, the first input of which is connected with the second input of the third element OR, with the inputs of the installation of the counter, the divider is often 12 you, with the control inputs of the first and second shift registers and with the sixth output of the synchronization unit, the fourth output of which is connected to the third input of the seventh element I, the first input of which is connected to the forward output of the first trigger and through the delay element to the first input of the fifth element And, the output connected to the input of the frequency divider, the output of which is connected to the second input of the second element OR, the output of which is connected to the input of the converter analog - pulse duration, the output connected to the first input is fourth And, the output of which is connected to the first input of the first OR element, the second input of which is connected to the “output of the sixth element AND, the second input of which is connected to the output of the second adder-subtractor and to the information input of the second shift register, the synchronization input of which is connected to the synchronization input the first shift register, the output connected to the second information input of the first adder-subtractor, the first control input of which is connected to the output of the second element And to the first control input of the second the subtractor of the subtractor, the second control input of which is connected to the same input of the first adder-subtractor and to the output of the fifth OR element, the first input of which is connected to the output of the seventh And element, the second input of which is connected to the inverse output of the second trigger, the reset input of which is connected to the output the third OR element and the reset input of the first trigger, the installation input of which is connected to the first input of the second OR element, and the output of the fourth OR element is connected to the reset input of the third trigger, the input is set which is connected to the first input of the third element OR, the output of the eighth element I, is connected to the information input of the counter, the outputs of the bits of which are connected to the inputs of a group of display elements, the output of the first element I is connected to the second input of the fourth element I and to the first information input of the second adder -calculator, the second information input of which is a connection13131 not with the release of the second shift register. 2, The device according to claim 1, 1, 1 and 2; that is, the synchronization unit contains oscillators, a frequency divider, a delay element, the first and second elements are NOT, the first and second keys, and the output of the pulse generator is connected to the input of a frequency divider and is the second output of the sync block, the output of the frequency divider is connected to Phage.2 114 the inputs of the first key, the delay element and the first element are NOT and are the fifth output of the synchronization unit, the input of the second element is NOT connected to the zero potential bus, and the output is connected to the input of the second key, the output of which is the sixth output of the synchronization unit, the outputs of the first the key, the delay element and the first element are NOT the first of the third and fourth outputs of the synchronization unit, respectively. U yV (i-e) Fig.Z Compiled by E. Vlasov Editor E. Kopcha Tehred L. Serdvkova Order 1889/43 Circulation 864 Subscription VNIIPI USSR State Committee for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., 4/5 Production and printing company, Uzhgorod, Projecto st., 4 Proofreader G. Reshetnik