SU1056220A1 - Device for linearizing characteristics of transducers - Google Patents

Abstract

A DEVICE FOR LINEARIZATION OF CHARACTERISTICS OF MEASURING CONVERTERS, containing a subtraction and summation unit, a counter and a switch. The first and second outputs of which are connected respectively to the first D4 and the second inputs of the subtraction and summation unit, the third input of which is the input argument of the device, and the output is connected to the input of the counter connected by the discharge outputs to the corresponding information inputs of the switch, which In order to simplify the device, it contains a sequential memory operative block, the sample input of which is connected to one of the discharge outputs of the counter, the outputs are connected to the corresponding the control inputs of the switch, and the information inputs are in the input inputs of the device linearization coefficients.

Description

The invention relates to measurement and computing technology and is intended for use in multi-channel measurement systems with various types of measurement transducers having non-linear transfer characteristics. A device for linearizing the characteristics of the measuring transducers is known, which contains a block for the subtraction and summation of pulses, two Counters, a switching matrix, a decoder for the approximation sections and a frequency divider l. The disadvantage of the device is that it works with the same type measuring., Converters having the same nonlinear characteristics. The closest in technical essence to the invention is a device containing a subtraction and sum block, two counters, a frequency divider, a switch, The first and second outputs of which are connected, respectively, with the first and second inputs of the subtraction and summation unit whose third input is the information input of the device, the output of the subtraction and summation unit. with the input of the first counter, the first output of which is connected to the Switch's information input, the second output of the first counter connected With the input of the frequency divider, the output of which is connected to the input of the second counter, the lower bits of the address input of the permanent memory are connected to the output of the second counter of the constant output the memory block is connected to the control input of the switch, the higher bits of the address input are connected to the control input of the device. The disadvantage of this device is the relative complexity and difficulty of using it when replacing measuring transducers. The aim of the invention is to simplify the device. The goal is achieved by the fact that a device containing a calculator and a summation unit, a counter and a switch, the first and second outputs of which are connected respectively to the first and second inputs; the subtraction and summation unit, the third input of the terminal is the input argument of the device, and the output is connected to the input of the counter connected to the corresponding information inputs of the switch by the discharge outputs; it contains an operational memory: a sequential action unit, the sample input of which is connected to one of the the counter outputs, the outputs are connected to the corresponding KbMMMyTatopa control inputs, and the information inputs are the input inputs of the device linearization coefficients. FIG. 1 shows a block diagram of the device} in FIG. 2 - switch circuit is functional; in fig. 3 is a functional block and subtractor circuit. The device (Fig. 1) contains a block 1 of reading and summing, the argument input of which is connected to the output of the parameter converter to the number of pulses (not shown), and the output with the input of counter 2. The outputs of the counter 2 are connected to the corresponding information inputs of the switch 3, the first and second the outputs of the switch 3 are connected to the first and second inputs of the subtraction and summation unit 1. One of the discharge outputs of the counter-2 is connected to the sampling slot of the operational storage unit 4 of sequential operation, the output 5 of the unit 4 is connected to the control input of the switch. The information input 6 of block 4 is connected to the input of the input linearization coefficients of the device. va. Switch 3 (FIG. 2) contains a group of differentiating chains 7-12, the inputs of which are information inputs of switch 3. The outputs of differentiating chains 7-12 are connected to the inputs of elements 13-18, the second inputs of which are control inputs of switch 3 The outputs of the elements And 13-18 are connected to. the inputs of the element OR 19, the output of which is the first output of the switch 3. One of the control inputs of the switch 3 is connected to the buffer amplifier 20. The output of the buffer amplifier 20 is the second output of the switch 3. Block 1 subtraction and summation (Fig. 3) contains element 21, one of the inputs of which is connected to the third input of block 1. To the third input of block 1, the first input of element 22 and the clock input of the trigger 23 are connected. The second input of element 22 is the second input of block 1 of subtraction and summation, and the third input element And 22 is connected forward output flip-flop 23. The flip-flop inverse output 23 is connected to the second input of AND gate 21 and input of the flip-flop 24, the other input of which is the first input of the summing and subtracting 1. The direct output of the trigger 24 is connected to the input of the trigger 23. The output of the AND 21 element is connected to the clock input of the trigger 25, the output of which is connected to the first input of the OR element 26, the second input of which is connected to the output of the R 22 element, and the output is the output of the subtraction unit 1 and summation.

The device works as follows

- In the operative storage unit 4 of the sequential operation, linearization coefficients are inserted for the next transformation. During the signal conversion by the linearization device, to the input of block 1 of the subtraction and summation from the converter, the parameter — the number of pulses (not shown) receives a sequence of pulses. At the beginning of the conversion, the output of block 4 is given a code corresponding to the first section of the piece-linear approximation of the initial nonlinearity, carried out by this device. This code goes to the control inputs of the switch 3. It allows the passage of the corresponding number of pulses generated at the Outputs of counter 2 to the inputs of subtraction and summation. This number of pulses is added to the sequence of pulses; the parameter from the transducer is the number of pulses or is subtracted from it. As a result, a linearized pulse sequence at a given approximation area is fed to the input of counter 2. When a certain number of pulses arrives at the input of the counter 2, corresponding to the length of one approximation area, a pulse is generated at one of the discharge outputs of the counter 2, which is fed to the input of the sequential storage unit 4. In this case, the output of block 4 receives the code corresponding to the next approximation area, and the device operates in the same way as the first approximation section.

The bit output of counter 2, to which sample input of block 4 is connected, determines the length of the approximation section, and the length of the section in the scale of the linearizer output parameter is 2, where N is the bit number of counter 2f to which sample input of block 4 is connected.

The information inputs of the switch 3 (FIG. 2) receive pulses from the outputs of counter 2. By transferring the bits of counter 2 to one state, the differentiating chains 7-12 produce pulses, passing through AND 13-18 to the inputs of the OR 19 and on the first input of switch 3 is determined by the logic levels at the corresponding control inputs of the switch, the number of pulses that pass to the first output of switch 3 during the counter 2 cycle is equal to the code received at the control inputs of switch 3. To one of the controls The input inputs are connected to the input of the buffer amplifier 20i. The level of the signal coming from the buffer amplifier 20 to the second output of switch 3 determines whether the output pulses of the switch are added to the input pulse sequence in block 1 of the subtraction and summation or prohibit the passage of the corresponding number of input pulses sequences.

Block 1 subtraction and summation

(Fig. 3) works as follows.

Before starting work, it is necessary to set trigger 23 to the zero state. The input of block 1, which is the information input of the device, receives a pulse sequence from the parameter converters into the number of pulses, the frequency of which is divided into two trigger 25 and fed through the OR 26 element to the output of block 1. When it arrives at the first input of block 1 pulses the output of the switch 3, the trigger 24 is set to B a single state. A logic unit that enters the trigger 23 from the trigger 24 output allows the trigger to be switched.

23 in one state. At the same time, the logic zero level, received from the inverse output of the trigger 23 to the input of the trigger 24, resets the trigger 24 to the zero state. Wherein

the level of logical zero coming from the inverse output of the trigger 23 to the input of the trigger 24., resets the trigger

24V zero state. The pulse formed at the inverse output of the trigger 23 during the period of the input frequency prohibits the passage of one pulse from the input of block 1 through element 21 to the input of trigger 25. The logic level at the second input of block 1 of the subtraction and summation determines the operation mode of the block If there is a logical zero at the second input (reading mode), the pulse sequence formed at the output of trigger 25 through the OR element 26 passes to the output of block 1. The output sequence of block 1 corresponds to the subtraction of a single pulse from the input pulse sequence. If on the second block 1 there is a logical unit (pending mode), then the pulse generated at the direct output of trigger 23 allows the output pulse of the output sequence to be passed to the element E 22. The impulse formed in this way from the output of the element And 22 is fed to the input of the element OR 26 and is added to the pulse sequence formed at the output of the trigger 25. The resulting yulpulsny sequence is sent to the output of block 1. In the absence of

the pulses at the first input of block 1 of the subtraction and summation, independently oh the signal level at the second input of block 1, the pulse sequence arriving at the information input passes through the element 21 and divides 5 into two on the trigger 25 and passes to the 1 output of block 1 through the element OR 26,

The invention simplifies the operation of the device when replacing the measuring

converters in multichannel measuring system.

 The use of the invention will have a significant economic effect due to the cheapening of the linearization device against the existing one, and also due to the elimination of the process of writing the linearization coefficients in the permanent storage unit.

Claims (1)

class G, About F 15/20, 1981 (prototype). . DEVICE FOR LINEARIZING THE CHARACTERISTICS OF MEASURING TRANSFERS · BATTERIES, containing a subtraction and summing block, a counter and a switch, the first and second outputs of which are connected respectively to the first and second inputs of the subtraction and summing block, the third input of which is the input of the device argument, and the output is connected to the input of the counter connected by bit outputs to the corresponding information inputs of the switch, characterized in that, in order to simplify the device, it contains a random access memory block investigative action, the input of the sample of which is co-. is dined with one of the discharge outputs of the counter, the outputs are connected to the corresponding control inputs of the switch, and the information inputs are g inputs of input of the linearization coefficients of the device.