SU1086424A1 - Translator from binary code to binary-coded decimal code and vice versa - Google Patents

Abstract

BINARY CONVERTER BINARY-DECIMAL AND BACKWARD containing the binary code register, binary-decimal code register, adder, equivalent storage unit, the output of which is connected to the first information input of the adder, pulse generator, first and second elements AND, OR element, different by the fact that, in order to improve the speed, the first and second multi-bit switches, the first, second and third one-bit switches, a counter, a decoder, a trigger and an NAND element, and an accumulator The equivalents are binary, the outputs of the counter are connected to the bit inputs of the decoder and the storage unit of equivalents, the outputs of the decoder are connected to the first group of information inputs a register of binary-ten key code, the outputs of which are connected to the inputs of the NAND element and the first group of information inputs of the first a multidisk switch, the second group of information inputs of which is the first group of information inputs of the converter, the input of which is connected to the first control by the moves of the first and second one-bit switches, the first input of the OR element and the inhibiting input of the decoder, the transfer output of the adder is connected to the control input-decoder and the information input of the first one-bit switch, the second control input of which is connected to the binary - a local code, the second group of information inputs of which is connected to the outputs of the first multi-bit switch, the pack (the equal input of which is connected to the output of the trigger connected to (The control input of the second multi-bit switch and the first control input of the third one-bit switch, the second control path of which is the input of the initial installation of the converter and connected to the reset inputs of the trigger, counter, registers of the binary and binary-decimal codes, outputs which are respectively the first and second groups of information outputs of the converter, the second group of information inputs of which are connected to the first information inputs of the second multi-bit switch, the second) e informational inputs of which are connected to the outputs of the adder, and the outputs are connected to the informational inputs of the binary code register, the input of which is connected to the output of the first element And, the first and second inputs of which respectively

Description

but connected to the outputs of the first and third single-digit switches, the information input of the third single-digit switch is connected to the output of the pulse generator connected to the counter input of the counter, the input of the pulse generator is connected to the output of the second single-bit switch connected to the trigger input, and is input the end of the conversion of the converter, the output of the element is NOT connected

The BTopbiM control input of the second one-bit switch, the information input of which is connected to the output of the second element I, whose inputs are connected to the outputs of the binary code register, the input of the record of the register of the binary-decimal code is connected to the output of the element OR, the second input of which is connected to the output of the third a one-bit switch, the output of the binary code register is connected to the second information input of the adder.

The invention relates to the field of digital computing and can be used in specialized devices and computers.

A known binary-to-decimal converter and vice versa comprising a binary number register, a binary-decimal register, a driver of equivalents, a switch of equivalents, a one-bit adder and a control block.

The disadvantage of this converter is the low speed, which is a consequence of the sequential processing of the bit values. The closest to the proposed technical essence and circuit design is a binary code converter into binary-decimal and binary-decimal code into binary, containing a binary number register, a block of binary-decimal equivalents, a binary-decimal: adder decimal numbers, pulse distributor, comparison circuit, pulse generator, first and second elements AND, element OR, element NOT, first, second, third and fourth group of elements AND, we will take the outputs of the pulse distributor connected to odes first and second group of AND gates to the second inputs of which are connected outputs bit binary register rows, and outputs components of the first and second groups are connected to the inputs of the block of binary-coded decimal equivalents, which yields to Con cheny inputs the binary coded decimal

adder, the outputs of which are connected to the inputs of the register binary-decimal numbers C 2 3.

The disadvantage of this converter is the relatively low average conversion rate in the binary-to-decimal conversion mode associated with sequential polling of all bits of the binary number.

The aim of the invention is to increase the speed of the converter.

The goal is achieved by the fact that a binary-to-binary-decimal converter and vice versa containing a register, a binary code, a binary-decimal code register, an adder, an equivalent storage unit whose output is connected to the first information input of the adder, a pulse generator, the first and the second AND elements, the OR element, the first and second multi-bit switches, the first, second and third single-bit switches, the counter, the decoder, the trigger, and the NAND element, are introduced, the adder and the equivalent storage unit S are binary, the counter outputs are connected to the bit inputs of the decoder and the storage unit of equivalents, the outputs of the decoder are connected to the first group of information inputs of the binary-decimal code register, the outputs of which are connected to the inputs of the AND-NAND element and to the first group of information inputs of the first multi-bit switch , the second group of information inputs of which is the first group of information inputs of the converter, the control input of which is connected to the first control inputs of the first and second one the main switches, the first input of the OR element and the forbidding input of the decoder, the transfer output of the adder is connected to the control input of the decoder and the information input of the first one-bit switch, the second control input of which is connected to the output of the higher bit of the register of the binary-decimal code, the second group informational inputs of which are connected to the outputs of the first multi-bit switch, the control input of which is connected to the output of a trigger connected to the control input of the second multi-bit the switch and the first control input of the third one-bit switch, the second control input of which is the input of the initial setup of the converter and is connected to the reset inputs of the trigger, counter, binary and decimal code registers, the outputs of which are respectively the first and the second groups of information outputs of the converter, the second group of information inputs of which is connected to the first information inputs of the second multi-bit switch, the second information inputs of which are connected to Connected to the outputs of the adder, and vspdsody connected to the information inputs of the binary code register, the recording entry of which is connected to the output of the first element And, the first and second inputs of which respectively-40

but connected to the outputs of the first and third single-digit switches, the information input of the third single-digit switch is connected to the output of the pulse generator connected to the counter input of the counter, the input of the pulse generator is connected to the output of the second single-bit switch connected to the trigger input, and is the output the conversion end of the converter, the output of the NAND element is connected to the second control input of the second one-bit switch, whose information input is connected to you Odom second AND gate, whose inputs are connected to the binary outputs of the register, record entry

At the input terminal 23 of the converter, a high potential is established before the supply of the number code. To the information input 18, the converter supplies the register of the binary-decimal code connected to the output of the OR element, the second input of which is connected to the output of the third one-bit switch, the output of the binary code register is connected to the second information input of cyviMaTopa. The drawing shows a structural diagram of the proposed Converter. The converter contains multi-bit switches 1 and 2, trigger 3, element 4, binary code register 5, binary equivalent storage block 6, binary adder 7, single-bit switches 8-10, element 11, pulse generator 12, counter 13, element OR 14, element AND-NOT 15, register 16 of the binary-decimal code, decoder 17. Switch 1 is designed to transmit inverted binary code to register 5 from information input 18 of the converter or direct code from the output of adder 7. Switch 2 transmits code from information input A code 19 converter or from the outputs of the register 16 of the binary-decimal code. The outputs of registers 5 and 16 are the first 20 and second 21 groups of transducer outputs, the output 22 of which is the output of the conversion end. The control input 23 sets the selection of the conversion law, and the input of the initial installation 24 performs the preparation of the converter for operation. The proposed Converter works as follows. In the binary / number conversion mode, double-decimal to control-, with binary code. The strobe arriving at the converter input 24, with the leading edge, sets the registers 5 and 16 and the counter 13 to the zero state. With the falling edge of the strobe signal, the binary code supplied via converter input 18 is entered into binary code register 5, trigger 3 is switched to the one state, allowing the strobe signals from the generator 12 to pass through the one-bit switch 9 and the And 4 element to binary code register 5, and sending the result of the subtraction from the output of the adder 7 through the switch 1 to the input of the register 5. The high potential at the control input 23 allows the signal to pass from the output of the transfer of the adder 7 through the switch 8 to the input of the And 4 element which generates a signal for entering information into register 5 according to the result of the subtraction. The second switch 10 at a high potential at the control input is set to pass a signal from the element 11 to the input of the generator 12 pulses, and the same potential at the control input 23 permits the operation of the decoder 17. The proposed converter allows the use of the same binary codes equivalents in both conversion modes, so the binary code, the pass through switch 1, is inverted. After entering the binary code into register 5, the generator of 12 pulses is turned on. The counter 13 forms the first sampling address of the binary equivalent from the block, 6 storage equivalents. The binary equivalent of block 6 is fed to the first information input of adder 7, the second information input of which is fed to the inverted code of the binary number being converted from the register 5 output. In the sender 7, the binary equivalent is subtracted from the number being converted, and if the subtraction has a negative result as evidenced by the high potential at the transfer output of the adder, the binary code of the number to be converted remains in register 5 unchanged, since the passage of the strobe signal to the input of the register 5An element 4 is prohibited by a zero potential from the output of the one-bit switch 8. The corresponding bit value of register 16 also remains zero, since the high potential at the transfer output of the adder 7 prohibits the formation of a low potential of the decoder 17. The counter 13 forms the next binary equivalent address from block 6. If the subtraction again has a negative result, the process is repeated. In the equivalent storage unit 6, binary codes of numbers 1,2,4,8,10,20, 40,80,100,200,400,800,1000, 2000, 4000, 8000, etc. are stored. The number of stored binary numbers is determined by the width of the converted binary numbers. The subtraction of binary equivalents from the code of the number being converted starts with a larger binary equivalent, i.e. at the first address of block 6, a larger binary equivalent is stored. In case of successful subtraction of the binary equivalent from the code of the number to be converted, the output potential of the transfer of binary adder 7 is set to zero, which, arriving at the decoder 17, allows the formation of a setting signal in the unit state of the corresponding register bit 16. counter 13. The zero potential from the transfer output of the adder 7, the passage through the switch 8 to the input of the element 4, inverts and allows the passage of the strobe signal to the input of the register 5. Re ultat subtracting the output from the adder 7 via the switch 1 to the register zanosits 5. The process of calculating is repeated, but with the binary equivalents compared subtraction result already obtained in predschuschem calculating cycle. The conversion continues until the And 11 element detects a zero result in the register 5. In this case, the And 11 element and the switch to form the generator 12 turn off signal, stopping the formation of pulses at the output of the And 4 element. The same signal performs the trigger 3 translation to the zero state, providing a pass to the device of a new code for conversion and strobe of its entry. The readiness of the device to receive a new code is confirmed by the low potential established at the output 22 of the device. After the generator is turned off by a signal from the output of element 11, register 16 contains the binary-decimal equivalent of the binary number being converted. In the binary-to-binary number conversion mode, a zero potential is applied to the control input 23 of the converter, which inhibits the operation of the decoder 17, permits the signal passing through the switch 8 from the high bit of the register 16 to the input of the And 4 element, switches the second switch 10 to skip the ending signal conversions from the NAND 15 element. Information input 18, the converter is supplied with a binary-decimal number code, and the input 24 of the converter is supplied with a gate from the channel. The leading edge of the strobe is the initial setting (set to zero state) of registers 5 and 16 and counter 13. On the falling edge of the strobe signal, the binary-decimal code is written to the register 16. By the falling edge of the strobe signal, the trigger 3 is converted into a single a state that ensures switching of the switch 2 to inverting and skipping the code from the inverse of the register 16 to the information input of this register. The second information input of the converter is turned off. A high potential switch 9 translates to a skip signal from the output of the generator 12 to the strobe input of the register 16 through the element. OR 14, which is open to zero potential set at converter control input 23. After writing the binary number to the register 16, the pulse generator 12 is turned on. The counter 13 forms the first sampling address of the binary equivalent from the equivalent storage unit 6. The binary equivalent from the output of block 6 is fed to the first input of the adder 7, where it is summed with the code fed from register 5 to the second input of the adder 7. In the first cycle of operation of the device from the output of the register 5, the zero input is applied to the second input of the adder 7, since the register 5 is reset. The code from summator 7 through switch 1 is fed to the information input of register 5. The output of the high bit of register 16 controls the passage of the clock signal through element 4 to the gate input of register 5. In the case of a single value of the high bit of register 16, element 4 opens skip the gate pulse from the output of the switch 9, and the code from the output of the adder 7 is entered into the register 5 of the binary code. If the high order bit in register 16 is zero, then the contents of register 5 remain unchanged. In the next clock cycle, the code in register 16 is shifted by one bit towards the higher bits. The counter 13 forms the next sampling address of the binary equivalent from block 6. The contents of register 16 are constantly parsed to zero. In the case of zero in all bits of register 16, the unit potnitsial from the output of the element IS-NOT 15, the passage through switch 10, is inverted and turns off the generator 12, Ck, then the register 5 will contain the binary equivalent of the binary number written in the register 16. The proposed invention allows to increase the average speed of converting a binary number to a binary-decimal compared to a prototype device, in which a binary-decimal number is obtained after polling all bits of the binary code (fast The conversion of the converter prototype is determined by the binary number, the proposed device allows you to complete the conversion without generating zero values after the last significant digit of the binary number, i.e., reducing the conversion time by the number of cycles needed to form the remaining zero bits) - , to simplify the device of the converter by replacing the binary-decimal adder with a binary, smaller one, excluding the group of elements And and the comparison circuit (replacing two groups of elements And with an open m collector or tri-state at the output of two switches does not increase the cost of hardware, the introduction of the AND, NAND and switches compensated removal element group I); to simplify the coordination of the converter with specialized devices and processors of computers manufactured by industry (if in the converter-prototype in the conversion mode of a binary-decimal code to binary at the inputs of a binary-decimal number, the code must be kept constant, then the proposed converter after entering the codes into registers It works autonomously, confirming its readiness for the next cycle of operation by outputting a low potential signal to the channel).

The zeroing of the registers in the device prototype is performed by applying zero codes to the inputs of the device.

I

nineteen

18

L

/

/

f /

f6

that takes extra time. This disadvantage is eliminated in the proposed converter.

/four (

f:

L

l

f

12

-

7V

17

Claims (1)

Binary code to binary, decimal and reverse, containing a binary register, a binary-decimal register, an adder, an equivalent storage unit, the output of which is connected to the first information input of the adder, a pulse generator, the first and second AND elements, the OR element, characterized in that, in order to improve performance, the first and second multi-bit switches, the first, second and third single-bit switches, a counter, a decoder, a trigger and an NAND element are introduced into it, moreover, an adder and a storage unit the equivalents are binary, the outputs of the counter are connected to the bit inputs of the decoder and the equivalent storage unit, the outputs of the decoder are connected to the first group of information inputs of the binary-decimal code register, the outputs of which are connected to the inputs of the AND gate and the first group of information inputs of the first multi-bit switch, the second the group of information inputs of which is the first group of information inputs of the converter, the control input of which is connected to the first control inputs of the of the first and second one-bit switches, the first input of the OR element and the inhibitory input of the decoder, the adder transfer output is connected to the control input of the decoder and the information input of the first one-bit switch, the second control input of which is connected to the high-order output of the binary-decimal code register, the second group of information inputs of which 'connected to the outputs of the first multi-bit switch, the control input of which is connected to the' output of the trigger connected to (Control input of the second about a multi-bit switch and the first control input of the third single-bit switch, the second control input of which is the input of the initial installation of the converter. It is connected to the reset inputs of the trigger, counter, registers of binary and binary decimal codes, the outputs of which are, respectively, the first and second groups of information outputs of the converter, the second group of information inputs of which are connected to the first information inputs of the second multi-bit switch, the second information inputs of which are connected to the outputs of the adder, and the outputs are connected to the information inputs of the binary code register, the recording input of which is connected to the output of the first AND element, the first the first and second inputs of which are respectively connected to the outputs of the first and third one-bit switches, the information input of the third one-bit switch is connected to the output of the pulse generator connected to the counting input of the counter, the input of the pulse generator is connected to the output of the second one-bit switch connected to the installation input of the trigger, and is the output of the end of the conversion of the Converter, the output of the element AND is NOT connected to the second control input of the second one-bit switch, inform the input of which is connected to the output of the second AND element, whose inputs are connected to the outputs of the binary code register, the input of the binary decimal register register is connected to the output of the OR element, the second input of which is connected to the output of the third one-bit switch, the output of the binary code register is connected to the second information input of the adder.