SU1305692A1 - Information input device - Google Patents

Abstract

The invention relates to computational and information-measuring equipment and is intended to attach to a computer external devices (WU) with a matrix structure of information. The purpose of the invention is to expand the class of solvable tasks of the device by providing the possibility of connecting WU not only with a constant length of rows within the matrix (frames) of information, but also with a variable length of rows. The device contains information register and operation code register, row length counter and matrix length counter, control block, opcode decoder, pulse distributor, block of OR elements, two OR elements, three blocks of AND elements, three And elements, trigger, two delay elements, pulse generator and memory block. The trigger state determines the type of plug-in slave - with a constant or variable length of rows in the information matrix. In the first case, the length of the rows of the matrix} and the length of the matrix (the number of rows in the matrix) are formed in the process of entering the information matrix into the counters. In the second case, the row lengths are formed in the row length counter and stored in the memory block, and the matrix length is formed in the matrix length counter. After entering the matrix of information into the computer, the generated parameters of matrix 1 are entered. 2 Il. (O (L 00 o O1 O5 co

Description

113

The invention relates to information-measuring and computer engineering, in particular, to devices. you can enter information into a computer, and can be used to connect NIN to a computer with non-standard external devices (WU) with a matrix (personnel) structure of information in various automated research systems.

The aim of the invention is to expand the class of tasks of the device by providing work with frames of variable length information.

Figure 1 shows the block diagram of the device; Fig. 2 shows an example implementation of the control unit.

The device (Fig. 1) contains an information register 1, a register 2 of the operation code, counters 3 - 1 and 3 - 2 row lengths and a matrix length, control block 4 with inputs 5-7 and outputs 8-11, a decoder 12, a distributor

13 pulses, a block of 14 elements OR, 25 Noah information in the counters 3-1 and 3-2

blocks 15-17 of elements AND, elements AND 18-20, trigger 21, elements 22 and 23 of delay, elements OR 24 and 25, driver 26 pulses, block 27 of memory.

Control block 4 (FIG. 2) can be implemented as an operation decoder 28, elements 29 and 30, pulse generator 31, delay element 32.

The device works as follows.

Entering a matrix of functional information through a device in a computer is performed in two stages: input of functional information and input of a setup column of the matrix.

The input of functional information is always carried out in a corresponding way. After the setup column has been entered, the counters 3-1 and 3-2 are reset to the zero state by a signal from the outside (the reset circuits on the structure diagram are not shown). |

A setup column is entered by a sequence of two corresponding operations, if the prize of the setup column type when entering functional information has a single value (i.e., the row length of the matrix depends on the row number in the matrix).

40

In this case, the first input operation of the setup column is specified from a computer with a zero sign of the type of the tuning column and is entered into the EVC by the corresponding operation, the code of which is the prize-45 held by the counters 3-1 and 3-2, after the type of the tuning column is charged. why these counters are reset. They are barked into a computer device. If the input of functional information was performed with a zero value of the type of the tuning column type, after the completion of this operation, the matrix row length m is stored in the counter 3-1, and the matrix length n is stored in the counter 3-2. If the specified operation was performed with a single value, the contents of the cells are entered with cues of the type of tuning column-memory block 27, each of which is, then after its completion the matrix length n is stored in the counter 3-2, and the variable line lengths The most convenient computer uses only the contents of counter 3-2, in which the parameter n of the matrix was stored, i.e. the number of 5Q rows in the functional information matrix previously entered into the computer. The second entry operation of the setup column is specified from a computer with a single feature of the setup column type.

the lengths of the corresponding lines of the functional information previously entered into the computer were stored. On this after, nth block cells

nts in 1,2 ,. 27 memories.

The input of the tuning column, depending on the type of the tuning column in the functional information input operation, can be performed either by one or by a sequence of two corresponding operations, also specified from a computer.

The setting of the setting column is carried out by one appropriate operation, if the sign of the type of tuning column when entering functional information has a zero value (i.e., all parameters of the tuning column are constant within the same matrix of functional information). In this case, a setup column is entered from the computer with a zero sign of the setup column type and a setup column is entered into the computer with constant parameters of row and matrix lengths that are stored after entering the matrix, respectively. After the setup column has been entered, counters 3-1 and 3-2 are reset to the zero state by a signal from the outside (reset circuits are not shown in the block diagram).

A setup column is entered by a sequence of two corresponding operations if the type attribute of the setup column when entering functional information has a single value (i.e., the length of the matrix row depends on the row number in the matrix).

In this case, the first input operation of the tuning column is set from a computer with a zero sign of the type of the tuning column and the contents of counters 3-1 and 3-2 are entered into the ECM, after which these counters are reset. In 55, the contents of the cells of the memories of the memory block 27 are entered, in each of which

Further, the computer uses only the contents of the counter 3-2, in which the parameter n of the matrix was stored, i.e. the number of 5Q rows in the functional information matrix previously entered into the computer. The second entry operation of the setup column is specified from a computer with a single feature of the setup column type.

In this case, the first input operation of the tuning column is set from a computer with a zero sign of the type of the tuning column and the contents of counters 3-1 and 3-2 are entered into the ECM, after which these counters are reset. The contents of the cells of the memories of the memory block 27 are entered, each of which is

the lengths of the corresponding lines of the functional information previously entered into the computer were stored. On this after313

The completeness of the input of the tuning column in the PEM is completed.

Let us now consider in detail the operation of the device when performing input operations of functional information and input of a setup column with zero and one values of a feature of the type of a setup column.

When register 2 is zero, the operation code received from the computer and the tuning column type code, followed by a synchronization pulse at input 6 of block 4, are recorded by the output from output 8 into register 2 and trigger 21. To decrypt the zero state and the received code operation code from the output of register 2 is fed to the input 5 of block 4 and to the decoder 12.

Let the register 2 enter the operation information input code of functional information, and the trigger 21 is set to the zero state corresponding to the zero value of the sign of the type of the tuning column. Under the indicated trigger state 21, the memory unit 27 is turned off and does not respond to input signals, the element r1 19 is locked. By entering into the register 2 of the operation code for entering functional information, unit A on output 11 resets the matrix length counter 3–2, and the slave unit starts inserting functional information (matrix elements — counts) into the device accompanied by synchronization pulses and line start scanning pulses. matrices. These signals are received respectively at the information input of register 1, at input 7 of block 4, at the inputs of delay element 22 and element OR 25. Each pulse of the beginning of line delayed by element 22 sets the counter 3-1 of the line length to zero and, pass through the element OR 24, increases by one the contents of the counter 3-2 matrix length. The synchronization pulse at input 7, block 4, at output 9, enters functional information into register 1 and, with some delay, outputs a pulse to output 10. This impulse, after passing through delay element 23, increases the contents of counter 3-1 of the string length by one. (Note that the delay values of elements 22 and 23 are equal, and the pulse delay at the output 10 of block 4 relative to the synchronization pulse at the input

five

0

5 Q ,, g with

five

De 7 requires LL (strmalioG) operation of the counter 3-1 with simultaneous receipt of pulses for the start of line scanning and synchronization). Functional information from the output of the register 1 through the block 14 of the elements OR is output to the output of the device and then to the computer. After the input of the functional information matrix is completed, the WU stops issuing signals to the device inputs and issues an end-of-operation impulse to the second control input of the device, registers 1 and 2 are reset to zero, and in counters 3-1 and 3-2 the setting column of the transferred matrix is formed and stored (in the counter 3-1 - the length of the line, in the counter 3-2 - the length of the matrix). I

When performing an input of functional information with a single value of the type of a tuning column, the trigger 21 is set to one, allowing the memory 27 to work, opening the element AND 19 and locking the element 18. And in addition to the described process, when performing the operation of entering functional information with a zero value In this case, the sign of the type of the tuning column also records, for each pulse, the start of scanning the row of the matrix of the content of the counter 3-1 in the memory block 27. Obviously, by the time the next pulse of the start of the scan of the line arrives, the counter 3-1 stores the code of the length of the previous row of the matrix. This code is fed to the information input of the memory unit 27. The address of the write or read to the corresponding input of the memory unit comes from the output of the counter 3-2 of the matrix length. The impulse began to scan the line through the OR element 25 and is fed to the input of the imager 26, at the output of which a write signal is generated to the memory block 27. The duration of the recording signal must be such as to ensure reliable recording in block 27, i.e. the duration of the recording signal is determined by the speed of the memory. If the write signal at the output of the imager 26 is absent, then the block 27 is set to read mode. As mentioned, the values of the delays of the elements 22 and 23 should be equal to each other and chosen so that by the time of occurrence

of the delayed pulse of the start of scanning the line at the output of the delay element 22, the writing to the memory block 27 was completed. Note that the first pulse of the start of the scanning of the line records in block 27 at the zero address code of the initial state of the counter 3-1. Those. the code in the zero cell of block 27 does not make sense, and the lengths of 1,2, ..., (n-1) -th rows of the matrix will be written respectively in 1,2, ..., (n-1) -th memory cells ti, respectively, according to 2,3, ..., nth pulses of the beginning of a line scan. The length of the pth row is written to the pth cell of the memory unit by the pulse of the end of operation of the slave, coming from the second control input of the device through the OR element 25 to the input of the driver 26.

Thus, after completion of the input of functional information with a single value of the type of the tuning column in the counter 3-2, the matrix length is formed and stored, and the cells of the memory block 27 store the lengths of all matrix rows.

To enter the tuning column from the checks, ticks 3-1 and 3-2 from the computer in register 2 enter the operation code for entering the tuning column, and in trigger 21 - the zero value of the tuning column type attribute. According to the operation code decoded by the decoder 12, and

in the zero state of the trigger 21 signals the device output. After reading from the output of the element, And 18 enables the operation of the distributor of 13 pulses. According to the clock pulses coming from the computer to the synchronous input of the distributor 13 pulses, the distributor signals from its output to the inputs of blocks 15 and 16 of the elements I, provide the output of the contents of counters 3-1 and 3-2 to the computer, respectively, through the first 15 and second 16 blocks of elements I. The information output from the outputs of blocks 15 and 16 is output to the device via a block of 14 OR elements. After reading the information from counters 3-1 and 3-2, the latter are discarded.

E.SLI has entered the functional information matrix with a variable row size (a single value of the column type tuning characteristic), then to input the column tuning of such a matrix, two sets of cells of the block 27 must be executed successively, the input column of the tuning column is completed and after its completion the tuning column is fully entered.

40 in the computer.

The control unit 4 (Fig. 2) operates as follows.

The decoder 28 decrypts incoming code 5. Decoder

45 excites its first or second output if its input receives a zero code or an operation code for entering functional information, respectively.

50

55

When the zero code at the input of the decoder 28 allows the passage of a synchronization pulse from the input 6 of block 4 through the element 29 to the output 8 of the block. The impulse from the output 8 of block 4 enters into the register 2 (FIG. 3) the code from its information input.

When the register is set to 2, the input operation code of the functional information of the input of the tuning column. The first of them is performed with a zero value of the type of the tuning column and reads in

The computer contents of the counters 3-1 and 3-2, which is described. The second entry of the setup column is performed with a unit value of the type of the setup column, which

corresponds to a single state

trigger 21. According to the code of this operation, decoded by the decoder 12, and with a single trigger state 21, the signal from the output of the element And 19 opens the block 17 of the elements And and the element And 20, allowing the clock pulses through the elements And 20 and OR 24 hours the counting input of the counter 3 -2 The signal from the direct output of the trigger 21 also permits the operation of the memory block 27, which, when performing the setup column input operation, only works in the read mode specified by the corresponding signal from the output of the shaping device 26. For each sync pulse from the output of the I 20, the content of the counter 3-2 and the reading of information from the memory unit 27 at the address specified by the counter 3-2. Zero address reading does not occur. The read information from the output of the block 27 through the open block 17 of the elements AND and the block 14 of the elements OR the cells of the block 27 are inserted. This input of the input column for the tuning column is completed and after its completion the tuning column is completely entered.

in the computer.

The control unit 4 (Fig. 2) operates as follows.

The decoder 28 decrypts incoming code 5. Decoder

excites its first or second output, if its input receives a zero code or an operation code for entering functional information, respectively.

five

When the zero code at the input of the decoder 28 allows the passage of a synchronization pulse from the input 6 of block 4 through the element 29 to the output 8 of the block. The impulse from the output 8 of block 4 enters into the register 2 (FIG. 3) the code from its information input.

When installed in register 2, the operation input code of functional information of the customer from the second output of the decoder 28 permits the passage of 30 pulses from the output 7 of the block through the element AND. By installing the same potential, the shaper 31 sends a pulse to Bh xoA 1 1, which resets the counter of the matrix length 3-2 to zero (Fig.). Passed through the element And 30 pulses to the output 9 of block 4 are received directly, and to the output 10 through the element 32 of the delay. The delay is necessary for normal operation of the counter 3-1 of the length of the string, with simultaneous input of pulses from the external device — the beginning of the scanning of the string and synchronization of the exchange.

Claims (1)

Invention Formula An information input device containing an OR block, the output of which is the output of the device for connecting the computer information input, and the first input is connected to the output of the information register, whose information input is the device input for connecting the external output information, a string length counter and a matrix length counter, the outputs of which are connected respectively to the information inputs of the first and second blocks of the AND elements, the control inputs of the distributor connected to the output pulses, and the outputs, respectively, with the second output of the connected Respectively with the second and third inputs of the OR block, the decoder of the operation code, the input connected to the first input of the control unit and the output of the operation code register, whose input is the device input for connecting the information output of the computer, strobe inputs of the information register and the operation code register. to the first and second outputs of the control unit, the second input of which is connected to the synchronous input of the pulse distributor and is the input of the device to the third input of the trigger, information in od which is connected to an input device for coupling the data output of the computer, and a direct output 40 to the input authorization unit memory the write-read input of which is connected via a pulse shaper to the output of the second element OR, the first input of which is connected to the input of the first 45 of the delay element is the input for connecting the output of the start of scanning the matrix line of the external device, and the second input is the input of the device for connecting the synchronization output of the output signal of the end of the external computer output, the third input of the control unit the device, the first input of the third element I is connected to the output of the second element I, and the second input is connected to the input of the device for control is the device input for connecting the clock output of the external device, and the third the output is connected to the reset input of the account 55 of the synchronization output of the computer. W t5 20 25 thirty 056928 matrix length, characterized in that, in order to expand the class of tasks of the device by providing work with frames of variable length information, in it has a memory block, a third block of AND elements, a trigger, three elements: AND, two OR elements, two delay elements and a pulse shaper, the first inputs of the first and second AND elements are connected to the output of the operation code decoder, the second inputs of which are connected respectively to inverse and direct trigger outputs, and outputs respectively to the information input of the pulse distributor and the control input of the third block of elements I, the output and information input connected respectively to the fourth input of the block The OR elements and the output of the memory block, the information and address inputs of which are connected respectively to the outputs of the row length counter and the matrix length counter, the counting input of the matrix length counter is connected to the output of the first OR element, the first input of the third element connected to the output, and to the output of the first delay element and the reset input of the string length counter, the counting input of which is connected via the second delay element to the fourth output of the control unit of the trigger trigger, whose information input is soy a dinene with a device input for connecting a computer information output, and a direct output 40 with a memory block resolution input, the write-read input of which is connected via a pulse shaper to the output of the second element OR, the first input of which is connected to the input of the first 45 of the delay element is the input for connecting the output of the start signal scan of the matrix row of the external device, and the second input is 0U9 .1  3 / Editor S.Pekar Compiled by V. Vertlib Tehred A. Kravchuk Proofreader T. Kolb Order 1453/47 Circulation 673 Subscription VNIIPI USSR State Committee for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab ,, d, 4/5 Production and printing company, Uzhgorod, Projecto st., 4 JO Jz / // Phage. 2