SU1322297A1 - Information output device - Google Patents

Abstract

The invention relates to the field of computer technology and can be used to create a computer with memory. The aim of the invention is to expand the field of application of the device by providing bidirectional information exchange. The device contains the first trigger 2, the counter 3, the first, second elements OR 5, 6, the first generator 7 pulses, the first, second elements And 8.9, the Converter 10 codes, the first distributor 11 pulses, the driver 12 packs of pulses, the switch 17, the second , the third trigger 18, 19, the second pulse distributor 20, the pulse shaper 21, the third, fourth, fifth elements And 22, 23, 24 and the second pulse generator 25. The device provides a sequential recording and reading of information from the memory with automatic redirection. 3 il. from € N)

Description

And the invention relates to computing, can be used to create a computer with a memory and is an improvement of the device according to the author. St. No. 1270762.

The purpose of the invention is to expand the field of application by providing bi-directional information exchange.

FIG. 1 presents a structural

The memory device operates as follows.

With the arrival of the signal on bus 14, Output (Fig. 2p) unlocks 5 from counter 3, and shaper 12 forms a burst (Fig. 2S), the number of which corresponds to the number of times the output information (Fig. 26). Moreover, the first pulse in the bundle coincident device} in FIG. 2 and 3 - time gives in phase with the clock signal, the corresponding diagrams of its operation. The corresponding younger (senior) device (Fig. 1) contains an arithmetic logic unit 1 of an electronic keyboard computing machine (ECM), the first trigger 2, the score - t5 tick 3, memory block 4, first and second elements OR 5 and 6, first generator 7, first and second elements 8 and 9, code converter 10, first pulse distributor 11, which generated the frequency 20 of the first generator 7 (FIG. .2d, tel 12 bursts of pulses, group inputs, g, h). The first of these pulses and the input of which are respectively the first trigger 2 is set to the inputs 13 of the first group and the single state, the third reset by the first input 14 of the device, the second to the zero state (Fig.2l), the input 15 and the input of the second group 16 of the device and the Converter 10 code in the first

a number of output information, the second pulse coincides with the next bit signal, etc.

The leading edge of each pulse from the stack starts the distributor 11 pulses, which produces a pulse of pulses that are shifted relative to each other by one beat of the output

The switches, 17, the second and third triggers 18 and 19, the second pulse distributor 20, the pulse shaper 21, the third, fourth and fifth elements And 22-24, the second pulse generator 25.

The device works as follows.

In the initial state, the logic signal O on buses Output and Input blocked counter 3, shaper 12 bursts of pulses and the fourth and fifth elements AND 23 and 24. Thus, the second trigger 18 in case gives out the code as comma, in the second - the converted code of discharge output information of the arithmetic logic unit 1.

30 Signals (Fig. 2i), arriving at the counting input of counter 3 from the output of the second element OR 6, set the address of the bits of the number entered into memory block 4, the inputs of the address of which receive the address code of the number and the signals from the first element OR

Elements 8 and 9 will receive a resolution (comma signal). In this case, during the time of action of the bit signal ad5, information is recorded in the memory block 4. However, writing the code is only possible if

It is in the zero state and the block is 40 when the commanding output of 15 is arithmetic to the third element AND 22, from the output of the logic device 1 to the inputs of which the signal of the logical O arrives at the third input of the second element OR 6, and the switch 17 is blocked by the signal of the logical O which by -45 P bits of the number of the memory block 4, exited from the output of the fourth element, changes twice, AND 23 goes twice. Output information arithmetic and record signal (Fig. 2i, k). The first of the logical device 1 appears to record the code with bits at its outputs, comma, and the second write information to the converter of the 10 code, and the 50 corresponding to this bit of d-phases are pulse-coded. sync signals arithmetic logic unit 1 is fed to the inputs of the group

to the signal.

At the end of the last pulse of the driver 12 and the signal Vyshod, the obsolescence returns to its original state. For the device to function normally, the output signal must be at least two periods of the clock frequency,

shaper 12 packs of pulses and

to switch information inputs

17

When displaying information from the arithmetic logic unit 1 in block 4

The memory device operates as follows.

With the arrival of the signal on bus 14, the output (Fig. 2p) is unlocked from counter 3, and the driver 12 forms a burst (Fig. 2S), the number of which corresponds to the number of bits of the output information (Fig. 26). Moreover, the first impulse in the bundle of coincidence of the first generator 7 (figd, e, f, g). The first of these pulses is the first trigger 2 is set to one, the third is reset to the zero state (FIG. 2L), and the code converter 10 in the first

a number of output information, the second pulse coincides with the next bit signal, etc.

The leading edge of each pulse from the stack is the start of the pulse distributor 11, which produces a pulse of pulses that are shifted relative to each other by one beat of the output pulse.

In the case, it gives the code, in the second, the converted code of the output information of the arithmetic logic unit 1.

Signals (Fig. 2i), arriving at the counting input of counter 3 from the output of the second element OR 6, set the address of the digits of the number entered into memory block 4, the inputs of the number address of which receive the address code of the number and the signals from the first element OR

Elements 8 and 9 will receive a resolution (comma signal). In this case, during the time of action of the bit signal, after the comma 15 output of the arithmetic unit 1, the inputs P of the number of the memory 4 are changed twice, and the recording signal is received twice (Fig. 2i, k). The first signal records the code of the comma, and the second records the information corresponding to this bit.

when the output of the logical discharge bit is changed twice the signal of the recording by the signal is empty impingement, and W corresponds to

to the signal.

when from the output of the comma 15 of the arithmetic unit 1 to the inputs P of the bit of the number of the memory 4 is changed twice, and the recording signal is received twice (Fig. 2i, k). The first signal records the code of the comma, and the second records the information corresponding to this bit.

At the end of the last pulse of the driver 12 and the signal Vyshod, the obsolescence returns to its original state. For the device to function normally, the output signal must be at least two periods of the clock frequency,

Otherwise, the output of all the digits of the nformmation is not possible.

In the Input mode (Fig. 3), the device operates as follows.

In the initial state, the address code of the input number is sent to the address inputs of the number of the memory block 4 via the input bus 28 of the device. With the arrival at time tg of the Input signal, synchronized with the start of the second pulse 10 of the second distributor 20 pulses (Fig. Zp, t), the fourth and fifth elements AND 23 and 24 and counter 3, which are output to the address, are unblocked; The inputs of the digits of the block number 4, 5, mti arrive at this moment the zero code of the address of the younger (senior) digit of the input number. The leading edge of the third pulse (Fig. 3c, c) the second trigger 18 is set to 20 in one state, unlocking the third element I 22. From the outputs of the arithmetic logic unit 1, the information inputs of the switch 17 are supplied with clock signals, and to its 25 control inputs from the output of memory block 4 receives the code of the lower (senior) digit of the input number. At time t (Fig. 3N) from the first

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the output of the imaging unit 21 ZO pulses through the third element And 22 to the input of the prohibition of the switch 17 comes the resolution signal and a certain clock signal in accordance with the code of the discharge is fed to the corresponding input of the arithmetic logic unit 1. Over a period of time tj-t (Fig. W / h) in the arithmetic logic unit 1, a sync signal is captured (for example, for ALU 145 IP 7, 145 IP 12 this time is 2-3 sync periods), and in the time interval tj-tj, the arithmetic logic unit 1 performs the input operation of the first digit of a number. This time is determined by the speed of the arithmetic logic unit 1, and the sync signals at its outputs are absent at this time (Fig. 3m) and appear again only at the time tj (Fig. 3m), which indicates the end of the input of the discharge numbers in arithmetic logic unit 1. The third trigger 19 is installed 19 runs the second valve

20 pulses, the output of which starts the pulse shaper 21 (Fig. 3n, o, n). In this case, the third pulse 19 and the switch 17 are blocked by the first pulse of the second pulse distributor 20, and the second pulse (Fig. 3p) sets the code for the next bit of the input number at the outputs of counter 3, which is fed to the address inputs of the number of bits of the memory 4. From the output of the latter, the code of this bit enters the control inputs of the switch 17.

After the t-sync signals appear at a certain time tj-t (for example, for arithmetic logic units 145 of the t series, -t. 7-10 ms), arithmetic logic unit 1 is ready to enter the next digit number.

At time t, the switch 17 is unlocked, after which it is entered into the arithmetic logic unit 1 of the next digit number. Similarly, the remaining digits of the number are entered.

The signal from the first output of the pulse generator 21 (Fig. 3N) provides the necessary input delay for the digit, and the signal from the second output — using the third trigger 19 — triggers the second distributor 20 pulses only after the input of the previous bit has finished. This achieves maximum device speed when entering.

At the moment when the code 3 of the address of the last entered bit appears at the outputs of counter 3, a logical O signal appears in its transfer output (FIG. 3F), which blocks the fifth element AND 24. A third pulse from the output of the second distributor 20 pulses is the second trigger 18 is reset to O (Fig. 3i) and thereby prohibits the passage of pulses through the fourth element AND 22 to the input of counter 3.

Upon completion of input to the arithmetic logic unit 1 of the last digit of the number at time t,

It is in a single state, so (Fig. Sp, t) the signal Input drops - at time tj it is unblocked by a signal in C, blocking counter 3 and even the second and fifth elements And 23 and 24 , and pulses (Fig. Pro). By a signal, the device log returns to the initial 1 from the output of the third trigger state.

oh oo10 -, 5 20 o 25 35

40

ZO a. ). eating - 3222974

19 starts the second valve

20 pulses, the output of which starts the pulse shaper 21 (Fig. 3n, o, n). In this case, the third pulse 19 and the switch 17 are blocked by the first pulse of the second pulse distributor 20, and the second pulse (Fig. 3p) sets the code for the next bit of the input number at the outputs of counter 3, which is fed to the address inputs of the number of bits of the memory 4. From the output of the latter, the code of this bit enters the control inputs of the switch 17.

After the t-sync signals appear at a certain time tj-t (for example, for arithmetic logic units 145 of the t series, -t. 7-10 ms), arithmetic logic unit 1 is ready to enter the next digit number.

At time t, the switch 17 is unlocked, after which it is entered into the arithmetic logic unit 1 of the next digit number. Similarly, the remaining digits of the number are entered.

The signal from the first output of the pulse generator 21 (Fig. 3N) provides the necessary input delay for the digit, and the signal from the second output — using the third trigger 19 — triggers the second distributor 20 pulses only after the input of the previous bit has finished. This achieves maximum device speed when entering.

At the moment when the code 3 of the address of the last entered bit appears at the outputs of counter 3, a logical O signal appears in its transfer output (FIG. 3F), which blocks the fifth element AND 24. A third pulse from the output of the second distributor 20 pulses is the second trigger 18 is reset to O (Fig. 3i) and thereby prohibits the passage of pulses through the fourth element AND 22 to the input of counter 3.

Upon completion of input to the arithmetic logic unit 1 of the last digit of the number at time t,

Claims (1)

Invention Formula Device for displaying information on the author. St. No. 1270762, characterized in that, in order to expand the scope of application by providing bidirectional information exchange, a switch, second and third triggers, a second pulse distributor, a pulse shaper, a third, fourth and fifth And elements, and a second pulse generator are introduced into it, moreover, the output of the second pulse generator is connected to the clock input 10 the reset input of the third trigger and the first input of the fourth element I, the output of which is connected to the control input of the switch, the output of which is connected to the output of the device for connecting the data on an ECM data output of the third trigger connected to the start input of the second pulse distributor, the first input of the fifth element And the connecting with the output of the counter, the reset input of which is connected to the second inputs of the fourth, fifth And elements and the input of the device for connecting the output of setting the command of the impulse siemsp v, .c ..., ... the house of the second pulse distributor, 15 yes information of a PCR, output n .in rtLTr 4ArTUuoun UUftu nM TIUnHHTiTM ВХО the first, second, third outputs of which are connected respectively to the input of the pulse generator, the first input of the third element AND, the synchronization input of the second trigger, the output of which is connected to the second input of the third element AND, the output of which is connected to the third input of the second element OR, the first, second outputs of the pulse generator are connected respectively to 25 And is connected to the information input of the second trigger, the first and second information inputs of the switch are connected to the outputs of the device for connecting the ECM synchronization outputs group and the memory data output respectively, the installation input of the third trigger is connected to the ECM input synchronization output. - (Data - (Data U- Lanniv U- - ( the reset input of the third trigger and the first input of the fourth element I, the output of which is connected to the control input of the switch, the output of which is connected to the output of the device for connecting the data on an ECM data output of the third trigger connected to the start input of the second pulse distributor, the first input of the fifth element And the connecting with the output of the counter, the reset input of which is connected to the second inputs of the fourth, fifth And elements and the input of the device for connecting the output of the input command, .. yes information of ECM, output p of that elek .in rtLTr 4ArTUuoun UUftu nM TIUnHHTiTM VHO And is connected to the information input of the second trigger, the first and second information inputs of the switch are connected to the outputs of the device for connecting the ECM synchronization outputs group and the memory data output respectively, the installation input of the third trigger is connected to the ECM input synchronization output. m and about P /one P P 1 i f ti t, t, t tf (rig. J Compiled by S. Burukhin Editor N. Rogulich Tehred I.Popovich Proofreader A.Obruchar Order 2866/46 Circulation 672 Subscription VNIIPI USSR State Committee for Inventions and Discoveries 4/5, Moscow, Zh-35, Raushsk nab. 113035 Production and printing company, Uzhgorod, st. Project, 4