SU1302241A2 - Linear-circular interpolator - Google Patents

Abstract

The invention relates to the field of automation and computer technology, and can be used in computer numerical control systems. The aim of the invention is to increase the accuracy of interpolation along the contour of an arc with multi-bit increments due to the implementation of an algorithm with alternation of a sequence of second-order computations. The linear-circular interpolator contains a clock unit 15, a switch unit 16, a shift register 17 and in each coordinate channel the first adder 5 (6), the first register 1 (2), the multiplier 9 (10), the second adder 7 (8), the second register 3 (4), divisor 11

Description

11302241 2

The invention relates to the field. If registers 1 and 2 have w discharge automation and computer technology, each has, and for step H it is foreseen to be used in the system but k bits, then the digit of the programmed control will be (t + k) In registers, the machines are advanced 3 and 4 are stored in the sums of results by abstraction of a known device according to auth. hackles and t-discharge residue of 1149218..pieces 11 and 12. Dividers 11 and 12

The aim of the invention is to increase the content division of the interpolation accuracy by contour registers 3 and 4 by the arc radius R with the arc 10 circular interrogation or by the magnitude

Figure 1 shows a structural scheme for moving around contour 1 with the linear mapping of the proposed interpolator; on . interpolation.

Fig. 2 illustrates a clocking unit; in FIG. 3- The division is performed with an accuracy of the timing diagrams of the operation of the device up to k bits, i.e. k — discharges; 4 shows a switching unit. The f5 quotient is placed in the output register. The interpolator contains the first 1 and 2 dividers 11 or 12, and the t-bit and second 3 and 4 registers, the first 5 and the stats remain in the remainder register 6 and the second 7 and 8 adders, the multiplier-divider. The blocks of elements And 13 and 14, 9 and 10, dividers 11 and 12, the blocks serve to transfer the contents of m divisions And 13 and 14, block 15 tactics-20 rows of the remainder of dividers 11 and 12 per van, switch block 16, shear adders 7 and 8. Clocking unit 15 register 17, its output 18, inputs 19 and with the arrival of each clock signal 20, outputs 21 and 22 of the switching unit, input 36 generates a sequence, clocking unit 23-33 of the clocking unit, eleven pulses, input 34 of the switching unit, inputs 25 through lines 23-33 with circular inter- face devices 35 and 36, outputs 37 and 38, and seven pulses along the switching unit lines .23–25, 27–29, and 31 with a linear clocking inter block contains generations. The sequence of impulse 39, element 40, and the counter 41 of the pulses determines the sequence of pulses, decoders 42 and 43, and trigger-30 operations in the device. Block 16, controls 44 and 45, the control OR 46, the keys in the circular interpol mode are the AND 47 and. 48, inverters 49 and 50, .Dia connects the output of the divider 11 - ... element OR 51, elements AND 52-62, k-bit quotient from the bus 19 to the input elements OR 63-66.cummator 6 on the bus 22 and the output the interblock switch 16 contains an Y axis on the bus 38; the output of the inverters 67, six groups of elements AND 68-. the separator 12 is connected via bus 20 to 73, two groups of elements OR 74 and 75. The input of adders 5 via bus 21 and the device works by following the device bypass on the axis X via bus 37, at once.

In registers 1 and 2, in the initial connection of the linear interpolation mode, the coordinates are set to the coordinates 19 of the divider 11 are connected to the starting point X, Y of the arc at a circular 37, the output 20 of the divider 12 is connected to the wide interpolation or the magnitude of the 38, the connection to the buses 21 and 22 from the station on the X axis., Y in the area of the output of the dividers is not made, processing with linear interpolation. 45 registers 1 and 2 are entered in the values. In the process of circular interpolation, in X and Y displacements along the axes on the parts of these registers, the coordinates of e interpolation are contained, in the shear register-current point of the arc. In the process, the line 17 establishes the value of the step interpolation, the contents of the register I, which, on the bus 18, is fed to the channels 1 and 2 does not change .50 ° D1 of the multipliers 9 and 10. In dividers 11 and 12, the program sets the x 9 and 10, the value 1 is produced - the length of the section in-. multiplying the contents of registers 1 and terptions, in registers 3 and 4 are zeros. 2 by the value of H or H / 2 stored by lines 34 and 35 is set in shift register 17 (H is the Linear interpolation command. By an interpolation step along the contour). Be is each cycle signal on line 36; the block is the length of the step H V-1, where V is the 15-clock rate and produces a seven-feed rate; i const - duration-cycles. The first cycle on line 23 is the cycle of calculating the increments. multiplication mc x

313022414

on the second clock. The second clock on line 24 is the block of elements AND 14 on the adder 8 and sews the transfer of the contents of the t-bit d-record of the sum to the register 4. 13 on the summator on line 33 shift J right (dividing 7 and writing the sum to register 3. Third to 2) of the value of H in the shift register, tact 17 takes place de-17. The eighth clock cycle on line 30 allows the sum of the result of multiplying the transfer of the private divider 12 by the remainder of the division on the previous bus 21 to the input of the adder 5 ,. on the second step. By the fourth clock cycle, on the 27th line, the input of which is supplied contains the multiplication of Y. by N. Fifth / Wash register 1. The clock 28 line allows the recording on the line to allow the recording of the result of the summation of the content to the register 1. Next the output register 10 multiplying the clock cycles .9-12 along lines 23-26 of the bits of the remainder of the divider division, operations similar to 12 are performed. The sixth clock cycle on line 29 is the first 15 clock cycles. The twelfth is divided by 1. By the seventh so tacacton on line 31, the private divider on line 31 is the private divider 11c11 is transmitted via bus 38 to the input in-. the bus 19 is connected to the output busbar at the Y coordinate, and the frequency 37 of the x-switch unit 16, the active splitter 12 via the bus 37 to the splitter 12 from the bus 20, an under-20 run along the X coordinate.

connected to the output bus 38 of the block in even cycles of signal generation

switching along the Y axis. It starts from line 27 and goes to the positIn circular circular interpolation mode by 27.28,29,32,30,23,24,

the program in registers 1 and 2 is set at 25,33,26,27,28., 29.30 and 31. the X values are located, the coordinates in the interpolator are implemented following the starting point of the arc, in the shift the re-calculating calculations, the gist 17 is half the value steps - For linear interpolation of the interpolation along the arc H / 2, in the divider ...

11 and 12 - radius of the arc of the circle R., + 1 i} Sequence of the passage of the signal-30 vu.r. v-

0100K - L NtK - - LA-X |

fishing lines 23-33 depend on the number-t h i

,,,. ent {l (Y..H. R.,)} i

In odd cycles, the first YT clock cycle on line 23 multiplies Xa from "i-i to H / 2", which is fed to the second C for circular interpolation at the odd-input multiplier 9 from the output of the shift-register cycles 17. The second clock on line 24

permits the transfer of the t-bit OS-& ent (- (X .. entl |} + R.); tatka divider 11 through the element block., K i 2. J com And 13 on adder 7 and writing the sum fHl to the register 3. The third beat on the line i xi i + i

25 divisions are made along line 32Y Y

t1-and 1 i

left shift (multiplication

by 2) the values of H / 2 in the shear register., ent | - (Y. -I + R);

Three 17. Fourth cycle in line g

allows the transfer of the private divider yi4i .i

11 through block 16 clocking over bus i-i

22 to the input of the adder 6. To the second input M 1

adder 6 is connected to the output register pi-4-i i-i-i 2l x; + KJ

3 Y coordinates. In the same tick on

signal from line 26 is produced for- R X-entl - + R - 4Y -R

 i-fi L2J + 1

writing the summation result in re-.

gister 2, i.e. computes Y.Y, - + Xi + i - i + i

+ Ay. The fifth cycle of line 27 is used to multiply the contents of the circular interpolation in 4 of 2 by the value of N. The sixth cycle of the cycle

line 2S allows the transfer of t-different-%

the remainder of the remainder of the divider 12 through J + i

entflcY, ent {f. R);

entflcY, ent {f. R);

t-tse

increments that are calculated but not output by the device.

The input line 36 receives pulses 1 / G, which specify the computation cycle, along line 35, the Circular interpolation command, the output lines 23-33 are connected to the corresponding interpolator blocks (Fig. 1).

In the linear interpolation mode, the trigger 45 at the input R is set to O, which provides a choice of the decoder 42, the inputs of which are connected to the outputs of the counter 41, the outputs of both the decoders 42 and 43 are connected via

35

elements 52-62 to the output unit of the clocking unit. Outputs 26, 30, 32 and 33 are closed for signal passing and are in state 1. The block time diagrams are shown in FIG. With the arrival of the cycle pulse at input 36, the trigger 44 is set. At 1, the element 40 opens, through which the generator pulses 39 pass. The next pulse of the generator 39 increases the counting count by 41 per unit, the outputs of the descramble Circular Interpolation are also singed more than eight times (with, which always takes place) with a slight complication of txeMbi. In this case, the possibility of a linear approximation of a circle by straight segments is used fully, and the limit on the speed of interpolation of arcs of circles of small radii is almost eliminated.

thirty

rmula of invention

Ratio o42 The control signals appear successively, which are output on buses 23,24,25,27,28 and 29. With the arrival of the eighth pulse from the output 7 of the decoder 42 through the elements OR 51 and 60 the signal will pass to line 31. With the arrival of the ninth pulse output 8 of the decoder 42 through the inverter 50,

Linear-circular interpolator on auth.St. No. 1149218, which differs from the fact that, in order to increase interpolation accuracy along the arc contour, a shift register is entered into it, the first and second inputs of which are connected respectively to the nine and sixth outputs of the clock unit, the element Both 48 and element OR 46 pulse 50, the third input — with the second input — sets trigger 44 and the counter 41 into a half, and the output — with the third input O. Setting trigger 44 into O multipliers of both channels, one-odd pulse transmission the generator input of the clocking unit is connected to the torus 39 to the counter 41 via it 40 to the fifth input of the switching unit.

022416

coincide before the next pulse of the cycle arrives.

In the circular interpolation mode, the input 35 is fed with 1, allowing 5 signals to pass through lines 26,30, 32 and 33, and the signal passing through the And 48 element is prohibited. In odd cycles, the decoder 42 is allowed to work, even in the decoder 43,

fO which provide the necessary pulse sequences along lines 23-33. After the end of each cycle from the output 12 of the decoder 42 or 43, the signal through the element And 47 is fed 5 to the counting input of the trigger 45 and through the element OR 46 to the inputs R of the trigger 44 and the counter 41, setting them to. A. Trigger 45, by switching, connects a decoder 42 or 43 depending on the parity of the number of the d.d.

F o

With a double alternation of computational cycles, the methodical error of circular interpolation is periodic in nature with an amplitude of H / 16R, which is proved by the methods of the theory of difference equations and confirmed by computer simulation. The interpolation accuracy is increased by 8 R / H times.

The accuracy of circular interpolation is also more than eight times more efficient (with what always happens) with a slight complication of xeMbi. In this case, the possibility of a linear approximation of a circle by straight segments is used fully, and the limit on the speed of interpolation of arcs of circles of small radii is almost eliminated.

rmula of invention

Linear-circular interpolator on auth.St. No. 1149218, which differs from the fact that, in order to increase interpolation accuracy along the arc contour, a shift reUg is introduced into it

J5Vr-

KI g I I I I I M I t I I I I I M I M I I I I M I 1 1

23 2ff- 25 26 27 28 23 30 31 J2 33

Lg

Editor L.Gratillo

pLli. four

Compiled by I. Schweu Tehred L. Serdyukov a

Order 1215/46 Circulation 864 Subscription

VNIIPI USSR State Committee

for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., 4/5

Production and printing company, Uzhgorod, Projecto st., 4

i uz.d

Corrector. M.Pojo

Claims (1)

16, the shift register 17 and in each coordinate channel the first adder 5 (6), the first ', register 1 (2), the multiplier 9 (10), the second adder 7 (8), the second register 3 (4), the divider 11 (12 ) and the block of elements And 13 (14). The device is a linear-circular interpolator with multi-bit increments and alternating the sequence of calculation of increments during circular interpolation and storing residues in simple fractions with an additional shift register, in which the value of the interpolation step in the process of calculation is doubled, which allows implementing second-order circular interpolation algorithms . The circular interpolation error of the proposed device is periodic in nature with an amplitude ά J Н / 16R, where Н is the value of the interpolation step of an arc of a circle of radius R. Fully use the possibility of linear approximation of the circle.