SU1215090A2 - Linear-circular interpolator - Google Patents

Abstract

The invention relates to the field of automation and Batching technology, and can be used in computer numerical control systems. The aim of the invention is to improve the accuracy of circular arc interpolation. The linear-circular interpolator contains registers, adders, multipliers, AND units, a clock unit, a pulse generator, dividers, a switch, a linear interpolation unit, an accumulator, a switch unit. This invention combines two substantially different interpolation groups with constant pitch and multi-bit increments. The use of a linear interpolation block according to the method of evaluation function and the additional elements and blocks associated with it to an interpolator with multi-bit increments made it possible to eliminate the accumulation of errors, jumps, to significantly increase the accuracy of circular interpolation. In circular interpolation after calculating the myogordary increments, the position of the calculated point is corrected by linear interpolation in single steps from this point to the center of the circle. 3 hp f-ly, 5 Sh1 (L 01 o

Description

one

The invention relates to the field of automation and computer technology and can be used in computer numerical control systems.

The purpose of the invention is to improve the accuracy of circular arc interpolation.

This technical solution combines two significantly different interpolation groups: with a constant step and multi-bit increments. The use of a linear interpolation block by the method of the evaluation function and the additional elements and blocks associated with it to an interpolator with multi-bit increments made it possible to eliminate accumulation errors, jumps, significantly improve the accuracy of circular interpolation.

Fig. 1 shows the structural scheme of the proposed interpolator; in fig. 2 shows an execution circuit of a clocking unit; FIG. 3 shows an example of a linear interpolation block; FIG. 4 shows a switching unit;

The linear-circular interpolator contains the first 1 and 2, the second 3 and 4 and the third 5 and 6 registers, the first 7 and 8 and the second 9 and 10 adders, the smart speakers 11 and 12, the dividers 13 and 14, the first 15, 16 and second 17, 18 blocks of elements AND, clock unit 19, pulse generator 20, switch 21, linear interpolation unit 22, accumulator 23, switch unit 24, first 25, 26 and second 27, 28 outputs of dividers 13 and 14, respectively 29 -30, 31-33 inputs and 34-37 outputs of the switch unit, input 38 and outputs 39-44 of the clock unit.

Switching unit 24 contains AND 45-48 Link elements shown in the diagram provide the connection of buses 29 and 30 required for the interpolator to work correctly on output buses 35 and 36 in linear interpolation mode and in circular interpolation mode on buses 34 and 37 for transmission to adders 7 and 8, respectively.

The clock unit 19 includes the RS-trigger 49, the pulse generator 50, element 51, the pulse counter 52, the decoder 53. The input line 38 receives pulses that specify the computation cycleJ output buses 39-44 under 15090 2

are connected to the corresponding interpolator blocks (see fig. 1).

The linear interpolation block 22 contains the RS-flip-flop 54, the delay element 53, the And elements 56, 57, the registers 58, 59, the inputs 60, 6 and 62 of the block, the outputs 63, 64 of the linear interpolation block. The links of the linear interpolation block provide linear interpolation according to the method of evaluation function along the straight line, given by points with coordinates X, Y, O, O, O, where X, and CC are the coordinates obtained from the output of adders 7 and 8, according to direction

) 5 to the point with coordinates 0,0.

Switching block 24 also contains elements AND 65, 66, elements OR 67, 68, and linear interpolation block 22 contains blocks of elements AND 69 and

20 70 and accumulator 71.

FIG. 1 is designated: output 72 of accumulator 23 and output 73 of the pulse generator.

Element and interpolator blocks

25 contain m two-input elements And, where m is the block size. The outputs of the elements And form the output bus of the block, the first inputs - the first input bus, the second inputs - the second

30 input bus.

The device works as follows.

In registers 1 and 2, coordinates are set in the initial state.

35 starting points X, U arc at

circular interpolation or the magnitude of the displacement along the axis m Xg, Y in the area of mining with linear interpolation. In the process of circular interpol 40, the coordinates of the current point of the arc are contained in these registers; in the course of linear interpolation, the contents of registers 1 and 2 do not change. In multipliers 11 and 12, 45 computes the contents of registers 1 and 2 by the interpolation step of contour H, the step size H is determined by the given feed rate and the duration of the computation cycle t,

50 t, e, H V «&, and const. If registers 1 and 2 have m bits each, and K bits are provided for K bits, then the product width will be (t + k).

55 Registers 3 and 4 contain the sums of the contents of the corresponding multiplier 11 and 12 and m the least significant bits of divisible dividers 13 and 14, which are summed by adders 9 and 10. Divisors 13 and 14 divide the contents of registers 3 and 4 by the value of the arc radius R with circular interpolation or by the amount of movement along contour 1 at linear interpolation. The division is made with an accuracy of K bits, i.e. K - the bit quotient is placed in the output register of the divider 13 (or 14), and m - the bit remainder is stored in the register of the dividend. The blocks of elements 15 and 16 serve as the dp of transmitting the contents of the m low bits of the divisible dividers 13 and 14 to adders 7 and 8. Registers 5 and 6 store the increments of the coordinates 4 X and U Y. Clock unit 19 with the arrival of each clock signal input 38 generates at outputs 39-44 a sequence of six pulses that determine the sequence of operations in the device. The switching unit 24 in the circular interpolation mode connects the output of the register 5 to the input of the adder 8. to bus 7 and to the output of the interpolator along the y axis along the strip 36; the output of register 6 is connected to the output of the adder 7 via bus 34 and to the output of the interpolator along the X axis via bus 35. In linear interpolation mode, the output of register 5 is connected to bus 35, the output of register 6 to bus 36. In this mode of bus connection 34 and 37 to the outputs of registers 5 and 6 is not produced. These elements provide the calculation and increment of the coordinates increments on the CFL method with multi-digit increments.

In circular interpolation after calculating multi-bit increments, the position of the calculated point is corrected by linear interpolation in single steps from this point to the center of the circle. The len cip correction is shown in FIG. 5. After each step, the value of the evaluation function for the circle is calculated. Linear interpolation to the center of the circle ceases when the sign of the evaluation function for the circle changes. Linear interpolation is performed in single steps by a linear interpolation block 22, the registers of which receive the coordinates of the starting point of motion from adders 7 and 8, Switch 21 allows 215090

pulse propagation from generator 20 for maintaining linear interpol xsn. From the output of the 63 linear interpolation block 22 on the X coordinate pulses

5 are fed to the inputs of register 1 and register 5, reducing their content by one with the arrival of each pulse. At the same time, through the block of elements And 17 the addition of the value

10, the X coordinates of the accumulator adder 23, which stores the value of the evaluation function for the circle. Similar actions occur when calculating the coordinates

15 I on line 64, the pulses arrive at the inputs of register 2 and register 6, reducing their contents. With each pulse through the block of elements And 18 the contents of register 2 enters

20 accumulator 23. If the accumulator accumulator overflows (changing the sign of the evaluation function for a circle), switch 21 prohibits the passage of pulses from the generator

25 20 per linear interpolation block 22,

I

Linear interpolation mode. In this mode, the Xj and Y values are entered into registers 1 and 2 on the axes in the interpolation segment, the multiplier H and 12 is set to the multiplier H, in dividers 13 and 14 - divisor 1 (the length of the interpolation segment), registers 3 and 4 are zeros; in switch block 24, the linear interpol command is set to 35 with input 33. For each signal of the cycle at the input 38, unit 19 generates 6 cycles. The first clock cycle on line 39 permits the recording of the contents of register 1

40 in the input register of the multiplier 1I, after which the value of X {is multiplied by H, the second cycle on line 40 permits the transfer of the contents of the lower bits of the dividend body 45 through the block of elements 15 to the adder 9 and the sum is written to the register 3, the third clock cycle 41 allows writing the contents of register 3 to the register of divisible divisor 13, after

50 for which the division operation is performed and the division result is recorded. In register 5, the analogic actions with the passage of the first three clock signals are performed in the second coordinate channel. The fourth and fifth cycles in this mode are not performed; the sixth cycle on line 44 permits the transfer of the contents of the register to 30.

Ditch 5 and 6 on the output tires 35 and 36, respectively. In linear interpolation mode, switch 2 is closed.

Circular interpolation mode. In this mode, registers 1 and 2 set the values of X, Y, - the coordinates of the starting point of the arc, in multipliers 11, 12 - the interpolation step H in, in dividers 13 and 14 the radius of the arc of the circle R. Operations performed by ticks , remain the same, and in linear interpolation mode. The fourth clock cycle on line 29 permits the transfer of the contents of register 5 through a switching unit 24 to bus 37 and summation with the contents of register 2 through an adder 8, as well as the transfer of the contents of register 6 through a switching unit 24 to bus 34 and summation with the contents of register 1 through an adder 7. At the same time, operations Y, -, Y; ± LU; ; X-, X,. ± LH; In the fourth cycle, the coordinates of the initial interpolation point are also recorded in the registers of the linear interpolation block 22 via lines 61 and 62. In the fifth cycle, the switch 21 is released and the pulse of the generator 20 is allowed to pass through the switch 2I to the input of the linear interpolation unit line 60 until the accumulator accumulator 23 overflows. In accumulator accumulator 23, the value of the evaluation function for the circle is stored. After calculating the increments according to the DCA method, the value H is added to the accumulator-accumulator. In the process of linear interpolation, in single steps, with a step along the X axis, the contents of register 1, register 5 decrease by one and change by the value of - (2 X +1) the contents of the accumulator accumulator 23. During the step along the Y axis, the content decreases by one. register 2, register 6 and is changed to greatness - (2 + 1) the contents of the accumulator adder. When accumulator 23 accumulator overflows, a signal appears, the key closes on line 72, interpolation stops, Circular interpolation signal is sent to the input of the switching unit in circular interpolation mode on line 31, therefore the sixth cycle on line 44 allows content to be transmitted - register 5 through switching unit

24 to the output bus, and the contents of the register 6 - to the output bus 35.

The following calculations are implemented in the interpolator.

In linear interpolation mode:

& X, (x, .H.R, .j,

., - Xi.e,

uY;. (j-H.R.,.; ,,. Yg.H.fi. -iY.g

where ent is an integral part of the expression;

R. are the remains of the i-ro calculation step.

In the mode of circular interpolation according to the CDA method. with multi-bit increments:

,

., tH.X; I r

. ./H X; -; R,

X; ,, X; ± yХ ;,

u ,.

After the calculation DCA, the value of the evaluation function changes (J; for a circle (initially AND 0)

Uu upn

In step linear interpolation, the evaluation function is

V, Y-Y -X

 Ul .1 1 + 1

If V "O, then a step is made along the Y axis, and

- V Vu, XiM,

U-UU, - (ZY +.),

Y-Y - i,

If V O, then a step is made along the X axis, and

V. V. -Y

HI + 1)

U-llu,), X-X - (.

71215090 .8

Step-by-step interpolation is terminated by chi or the absence of the impulse of the intersection when i o, after which it is taken from the accumulator 71

the previous cycle.

Hee

YU, V,

, - /; .-j /.

where i, j is the number of steps of linear interpolation along the axes X and Y, respectively.

FIG. 2 shows a clock unit circuit diagram 19. In the initial state, the control trigger 49 is in the state O, the element AND is closed, the counter is reset. With the arrival of a pulse to the input 38, the trigger 49 is set to 1, the element 51 opens, through which the generator 50 pulses pass. The next pulse of the generator 50 increases the contents of the counter 52, at the outputs of the decoder 53 sequentially, starting with line 39 and ending with line 44 control signals appear. After a signal on line 44, a signal appears on line 32, which sets the trigger 49 and the counter 52 to the initial state.

FIG. 3 shows a linear interpolation block diagram. The register 58 bus 61 loads the initial value of the X coordinate for step-by-step linear interpolation from the output of the adder 7 (see Fig. 1) after calculating the multi-bit increments using the CDA method. Similarly, the bus 62 loads the register 59 with the initial value of the Y coordinate. The accumulator 71 contains the value of the linear evaluation function V. Initially, YO, trigger 54 is in O. First, the impulse that comes along line 60 passes through the open element AND 56 to line 63 (step along the X axis) and opens the block of elements And 69; the register 58 is transmitted to the accumulator .71. Through the delay element 55, the trigger 54 is set to I, if there is no overflow in the accumulator, the trigger 54 remains in I and the next pulse passes through the element 57 on line 64, the contents register 59 through the block of elements And 70 enters the adder-drive 71, and the line 64 (step along the Y axis). The next impulse from line 60 passes to line 63 and 64, depending on the flow. 4 is a circuit diagram of a switching unit. In the circular interpolation mode on line 29 there is 1 (Circular interpolating). With

receipt of the fourth cycle on line 42 NII 42 bus 29 through a block of elements

And 65 is connected to the bus 37,. The bus 30 through the block of elements And 66 to the bus 34. When the sixth cycle enters the line 44, the bus 29 through the element 47 and the element JiJIH. 68 is connected to the output bus 36, and the bus 30 via an AND 46 block of elements and an OR 67 element to the output bus 35.

20

Claims (4)

Formula of the invented shadow I. Linear-circular interpolator containing in each coordinate channel connected in series the first adder, the first register, the multiplier, the second adder, the second register, the divider and the first block of AND elements whose output is connected to the second input of the second channel adder, as well as the clock unit and the switching unit whose first and second outputs are connected to the first inputs of the first adders the first and second coordinate channels respectively., the second inputs of which are connected to the output of the first register of its channel, the second inputs of the first registers are connected to the first input of the switching unit and to the first output of the clocking unit, the second output of which is connected to the second input of the divider in the channel, the third output to the second input of the second register and the second input of the block And, the first and second coordinate channels, and the fourth output of the clock unit is connected to the second input of the multiplier in each channel, characterized in that, in order to increase the interpolation accuracy along the arc contour, accumulator, serially connected generator, switch and linear interpolation unit and in each coordinate channel - the second block of elements And and the third register, the output of which is connected to the corresponding input of the switching unit, the first input of the register of each coordinate channel is connected to the corresponding output of the linear interpol block with the third input of the first register of its coordinate channel and with the first input of the second block of elements And, the second input of which is connected to the output of the first register, and the output to the corresponding input of the accumulator connected by the output to the second input of the switch, the third input of which is connected to the fifth output of the clock unit, the sixth output of which is connected to the third input of the switching unit, the second input of the third register in each coordinate channel is connected to the second output divider of the channel, the second outputs of the switching unit are the outputs of the linear-circular interpolator, the second inputs of the linear interpolation unit are connected to the output of the first adder of each coordinate channel. 2. Interpolator according to claim 1, which is based on the fact that the clock unit contains an RS flip-flop and a series-connected pulse generator, element I, pulse counter, and a decoder whose outputs are connected to the outputs of the clock unit, direct output The RS flip-flop is connected to the second input of the AND element, the 5th input is connected to the setup input of the clock unit, and the R input is connected to the H input of the counter and to the output of the last digit of the decoder. 3. Interpolator according to claim 1, which is based on the fact that the linear interpolation block contains the first register, the delay element, the first AND element and the second register connected in series, the first block of AND elements, the accumulator accumulator, the RS trigger , the second element And the second 5 block of elements And, the output of which is connected to the second input of the accumulator adder, the first input of the linear interpolation block is connected to the first input of the first and second input of the second And elements, and through the delay element to S RS-flip-flop input, direct output of which is connected to watts The first input of the first element And connected by the output to the second fS input of the first block of elements And to the corresponding output of the linear interpolation block. 4. The interpolator according to claim 1, that is, that the switching unit contains six AND elements and two OR elements, whose elevations are connected to the second outputs of the switching unit, and the inputs, respectively, to the outputs of the first, second, third and fourth And elements, the outputs of the fifth and sixth elements And are connected to the first outputs of the switching unit, the first input of which is connected 0 with the first inputs of the first, third and fifth elements And, the second input with the first inputs of the second, fourth and sixth elements And, the second input of the sixth element And connected to the second input of the fifth element And, the third input to the second inputs of the second, The third element And to the third input of the fifth element And, the second input of the first element And is connected to 0 with the second input of the fourth element And, the third input of the first element And connected to the third inputs of the second, third and fourth elements I. Fig.z LI QY Fy FIG. five Editor A, Veselovska Order 905/55 Circulation 837 Subscription VNIIPI USSR State Committee for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab, d. A / 5 Branch PPP Patent, Uzhgorod j. Project, 4 Compiled by I. Shvets Tehred A. Babinets Corrector S. Cherni