SU1295513A1 - Digital frequency synthesizer - Google Patents

Abstract

The invention can be used as a transmitter exciter with FM. The purpose of the invention is to increase the frequency range of the modulating signal and reduce the level of spurious FM. The device contains a controlled Mr. r 1, 1st frequency divider (DC) 2 with a variable division factor (CD), unit 3 sets the output frequency, frequency-phase detector 4, 1st filter (F) 5 low frequencies, the reference Mr. 6, 1st DF 7 with a fixed CD, phase modulator 15, integrator 16, source 17 modulating signal. The device includes the 2nd DCH 8 with a fixed CD, the phase detector 9, the 2nd F 10 low frequencies, the key 11, the synchronism indicator 12, the 2nd DF 13 with variable CD, F 14 high frequencies. 1 il. i (L Shtx. GS Sool 01 OO

Description

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The invention relates to radio engineering and can be used as an exciter transmitter with a frequency modulation.

The aim of the invention is to increase the frequency range of the modulating signal and reduce the level of spurious frequency modulation.

The drawing shows an electrical structural diagram of a digital frequency synthesizer (DSC).

The synthesizer contains a controlled oscillator 1, the first divider 2 frequencies with a variable division factor (DPDK), a unit 3 for setting the output frequency, a frequency-phase detector 4, the first low-pass filter 5 (LPF), a reference oscillator 6, the first divider 7 with fixed frequency - Vai division factor (DFCD), second DFCD 8, phase detector 9, second LPF 10, key 11, synchronization indicator 12, second DPDD 13, high pass filter 14, phase modulator 15, integrator 16 and modulating signal source 17.

CSCH works as follows.

In a transient mode, when switching from one frequency to another, when there is no synchronism, the key 11 according to the signal from the synchronization indicator 12 turns off the code of the second LPF 10. Synchronization is performed only with the help of an auto-tuning ring based on a controlled oscillator 1, the first The DPKD 2 frequency, phase detector 4 and the first low pass filter 5. After the synchronization mode is established, a signal is generated at the output of the synchronization indicator 12, which opens the key 11, as a result of which the component of the signal from the phase out th detector 9 through a second LPF 10, the key 11 and the filter 14 is supplied to a highpass second control input of the controlled oscillator 1.

Let, in synchronization mode, before switching on the key 11, the output signal of the controlled oscillator 1 is modulated by the parasitic frequency modulation voltage so that between the reference pulses from the main output of the second DCDCD 8 there were several periods of the parasitic frequency modulation voltage cobbles. Since, in synchronization mode, the pulses from the output of the first DPCD 2 are practically

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almost coincide with the pulses from the second output of the second DFCD 8 (i.e., at the inputs of the frequency-phase detector 4), the control voltage at the output of the frequency-phase detector 4 is approximately proportional to the phase error at that moment. Changes in the frequency of the controlled oscillator 1, associated with spurious frequency modulation in the intervals between the regulating pulses, are not processed in the phase locked loop. The frequency of the pulses from the first output of the second DFCD 8 is chosen two to three orders of magnitude higher than the frequency of the pulses from the secondary output (m. E. Comparison frequency) based on whether to skip high modulating frequencies or suppress the parasitic frequency modulation. In this case, if a sample-memory type detector 9 is selected, the division ratio of the second SCD 13 is assumed such that the period of pulses T at its output compared with the period of pulses T 2 at the intermediate output of the second DCDD 8 is determined by the ratio 0.5 T T : The most optimal solution

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T YTT,. This is explained as follows.

In the steady state synchronization mode, the pulses from the first output of the second, DFCD 8, arrive at the first input of the phase detector 8 (for example, sample-memorization type) and start its sawtooth generator. At the same time, these same pulses are fed to the reset input of the second PDKD 13 and are placed at the beginning of the count, i.e both dividers start counting at the same time. In this case, the fault (initial) pulse from the output of the second PDCD 13 does not enter the input of the phase detector 9. The pulse period at the output of the second PDCD 13 is approximately 3/4 from the start of the sweep. After this, the second DPKD 13 starts a new counting of pulses, but does not have time to complete it, since the impulse. from the second DFCD 8 resets the second DCD 13 and both dividers again start the counting over, and so on. Thus, in synchronization mode, in the absence of modulation by the information signal from the reference input and parasitic private modulation, the sampling pulse must always come and (1 day and

same point, sawtooth voltage i. At the output of the phase detector 9 or the second low pass filter 10, there is a constant voltage that does not pass through the high-pass filter 14 to the second control input of the controlled oscillator 1. If there is modulation of the information signal from the source 17 through the integrator 16 and phase modulator 15 reference pulses, coming from reference generator 6 through the first DFCD 7, or parasitic frequency modulation of the controlled oscillator 1, or both of them together, the sampling pulses arrive at different sawtooth points in the vicinity Approximately 3/4 of the reference pulse period. As a result, the output of the phase detector 9 generates a variable voltage, which passes the second LPF 10, the key 11 and the high-pass filter 14 to the second control input of the controlled generator 1 and changes its frequency so that parasitic frequency modulation (due to negative feedback) is significantly weakened (or completely eliminated), and modulation by the information signal remains completely in a wide frequency band from the minimum (almost zero) to such high level as necessary. At the same time, low modulation frequencies pass through the frequency-phase detector 4 and the first low-pass filter 5 to the first control input of the controlled oscillator 1, and the high frequencies go through the phase detector 9 and the second low-pass filter 10, the key 11 and the high-pass filter 14 The input of the controlled oscillator 1. This is explained by the fact that the controlled oscillator 1 is adjusted to the reference (reference) signal and the change of the reference signal due to the modulation of its information signal is repeated in it.

Thus, the simultaneous modulation of the controlled oscillator 1 by the information signal in a wide band and the elimination of the parasitic frequency modulation occur simultaneously.

When the output frequency changes, the first PDCD 2 and the second PDCD 13 are switched simultaneously at a command from the unit 3 of the installation, so that the period of the pulses at the output of the second PDCD 13 remains approximately 3/4 of the period

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reference pulses with pernog on the output of the second DFCD 8.

The application of the proposed CSC allows modulation of the information signal at the reference input in a wide frequency band from a minimum (almost zero) to as high as necessary.

It is possible to significantly reduce or completely eliminate the parasitic, frequency modulation associated with mechanical effects (vibrations, shocks, acoustic noise, etc.) on the equipment. At the same time, there is no need to fill the controlled generator 1 with special compounds and carefully absorb it. This leads to the forgiveness of manufacturing technology, increasing reliability.

Since in one period between the reference frequency pulses at the input of the frequency-phase detector 4 there is always an integer number of reference-pulse periods at the input of the phase detector 9, there is no discrete noise with a low frequency of comparison, which is determined by the specified frequency grid, in the synthesizer output signal and on the output of controlled oscillator 1 there are only discrete interference with high frequency, which can always be suppressed by the low-pass filter to the required value.

Claims (1)

Invention Formula A digital frequency synthesizer containing a looped controlled oscillator, a first frequency divider with a variable division factor, a frequency-phase detector and a first low-pass filter, successively, successively connected modulating source, integrator and phase modulator, serially connected reference oscillator and the first frequency divider with a fixed division factor, the output of which is connected to the second input of the phase modulator, as well as the unit for setting the output frequency, the output of which is connected with the installation input of the first frequency divider with a variable division factor, which is the first and the second, so that, in order to increase the frequency range of the modulating signal and reduce the level of the parasitic frequency modulation, successively a second frequency divider with a fixed division factor, a phase detector, a second low-pass filter, a key and a high-pass filter, a second frequency divider with a variable division factor, as well as a synchronization indicator, whose input and output are connected respectively Correspondingly with the output of the frequency-phase detector and the control input of the key, the input and the second output of the second frequency divider. With a fixed response factor. Editor O. Yurkovetska Order 627/61 Compiled by Y. Kovalev Tehred V. Kadar CorrectorM. Pojo Circulation 902 Subscription VNIIPI USSR State Committee for Inventions and Discoveries 113035, Moscow, Zh-35, Raushsk nab., 4/5 Production and printing company, Uzhgorod, Proektch street, - f, divisions are connected according directly to the output of the phase modulator and to the second input of the frequency-phase detector, the output of the high-pass filter is connected to the second input of the controlled oscillator, whose input is connected to the input of the second frequency divider with a variable division factor, the setup input, the reset input and the output are connected respectively with the output of the output frequency setting block, with the first output of the second frequency divider with a fixed division factor and the second input of the phase detector.