SU1285555A1 - Frequency synthesizer - Google Patents

Description

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The invention relates to radio engineering and can be used in radio engineering devices for various purposes, including radio communication devices.

The purpose of the invention is to increase the spectral purity of the output signal.

The drawing shows an electrical structural diagram of a frequency synthesizer.

. The frequency synthesizer contains the first 1 and second 2 and third 3 phase detectors, 4 frequency generator, first 5 and second 6 phasers, low pass filter 7, first 8 and second 9 controlled attenuators, first 10 and second And analog switches, first 12 and the second 13 sawtooth voltage generators (FPG), an inverting amplifier 14, a parallel adder 13, a counter 16, a decoder 17 and a trigger 18 with a counting input.

The frequency synthesizer works as follows.

A harmonic signal with a reference frequency is supplied to the first inputs of the first 5 and second 6 phasers, the second inputs of the first 5 and second 6 phasers, respectively, through the second 9 and first 8 controllers, receive a control signal from the respective second 13 and first 12 GPN.

The control signal of the first 3 and second 6 phase shifters is a voltage varying in pipiform form. If the phase increment at the output of the first 3 and second 6 phasers for the duration of the sawtooth signal T is 27 (, the spectrum of the output signal of the first 3 and second 6 phase shifters contains one component of the frequency FptFf, where F 1- / T, at the same time, the + sign corresponds to the positive derivative of the phase increment of the signal at the output of the first 3 and second 6 phase shifters, and the sign - to the negative. Thus, the formation of the output frequency of the frequency synthesizer taken from the outputs of the first 10 and second 11 analog switches carried out without using the generator, the voltage controlled oscillator, which is basic. source phase noise into sintezat

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frequency based on the phase locked loop.

An increase in the spectral purity of the output signal of the frequency synthesizer is achieved by installing the first 5 and second 6 phase shifters directly between the input and output of the frequency synthesizer. If, due to any destabilizing factors, the phase increment of the signal at the output of the first 3 and second 6 phase shifters during time T differs from 23g, in the spectrum of the output signal of the frequency synthesizer, the parasitic components appear in the frequencies that are FJJ. To stabilize the phase increment at the output of the first 5 and second 6 phase shifters equal to 2Jr per. the period T in the frequency synthesizer uses a control system in which the first 1 is included, in the second and third phase detectors, a filter 7, an inverting amplifier 14, a parallel adder 13, the first 10 and second I1 are analog keys, the first 8 and second 9 are controlled attenuators.

The control system works as follows.

The inputs of the first phase detector 1 are supplied with signals from the inputs and outputs of the first 3 and second 6 phase shifters. At the output of the first phase Detector 1, the phase difference of the signals at its inputs, i.e. information about the phase increment of the signal at the outputs of the first 3 and second 6 phase shifters. The characteristic of the first phase detector 1 is described by the cosL3 function, and the initial phase difference of the signals at the outputs of the first phase detector is 14 0. The phase difference corresponding to the instants of time when the control signal of the first 3 and second 6 phase shifters is zero. The difference in the phase increment of the signal at the outputs of the first 3 and second 6 phase shifters during the time from 2 Jt is reflected in the second 2 and third 3 phase detectors.

Consider the operation of the second 2 and third 3 phase detectors. Presumed we suppose that the phase increment of the signal over the period T is less than 271. The signal from the output of the first phase detector 1 is fed to the first input of the second phase detector 2 directly,

 and to the first input of the third phase detector 3 via an inverting amplifier 14, which can be performed, for example, on an operational amplifier. The second-INPUTS of the second 2 and third 3 phase detectors are supplied with reference signals from the second and third outputs of the decoder j, 17, respectively, shifted relative to each other by time. Besides, . the leading edge of the reference signal from the second output of the decoder 17 is shifted relative to the beginning of the sawtooth fO of the control signal of the first 5 and second 6 phase shifters by the time Tn / 4. The launch of the second phase detector 2 is performed by the falling edge of the reference signal, and the reset is performed at the moment 5 of the signal that characterizes the increment of the signal phase through zero with a negative derivative. The output of the second phase detector 2

Tote F, due to the final duration of the return stroke of the control signal by the first 5 and second 6 phase converters, two channels are used to form the output frequency, operating alternately. The first channel includes the first GPN 12, the first controlled attenuator 8, the second phase rotator 6 and the first analog switch 10. The second channel contains the second GPN 13, the second controlled attenuator 9, the first phase shifter 5 and the second analog switch 1I . In this case, the first 1 2 and second 13 FPs can be implemented, for example, on the basis of an integrator with a reset.

Consider the formation of the reference signals of the second 2 and third 3 phase detectors and commutation signals

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arrives on the account in the form of a binary

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information is allocated, the proportional 0 channels. From the output of the generator 4 to the difference of the phase shift of the signals at its inputs in time T „/ 4. The launch of the third phase detector 3 is performed by the falling edge of the reference signal, and the reset is performed at the moment of passing the NIN signal from the output of the inverting amplifier 14 through zero with a negative derivative. At the output of the third phase detector 3, the information is proportional to the phase difference of the signals at its inputs during 3/4 T.

The signals from the outputs of the second 2 and third 3 phase detectors are summed with different signs in the parallel adder 15, which can be performed, for example, on an operational amplifier.

The constant component is separated from the output signal of the parallel adder 15 by the filter 7, which is fed to the control inputs of the first 8 and second 9 controlled attenuators, and the slope of the sawtooth signal on the up-45 equalizing inputs of the second 6 and first 5 phasers changes. and therefore, the phase increment of the signal is adjusted to 2Ji over a period of.

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chick 16, performed counter.

The first and second bits of the counter 16 are connected to the input of the first and second bits of the decoder 17. The first, second and third outputs of the decoder 17 are respectively the outputs of its first, second and fourth bits.

The signals from the outputs of the second and fourth bits of the decoder 7 are used as reference signals of the second 2 and third 3 phase detectors.

In the first discharge of the decoder 17, a trigger control signal 18 is generated, which is turned on in the counting mode. On the first and second outputs of trigger 18, which are non-inverting and inverting outputs respectively, form IIPY channel control signals, while

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Claims (1)

Invention Formula A frequency synthesizer containing serially connected first and second phase detectors, a third phase detector, a frequency generator, a first phase shifter and a low-pass filter, and the first input of the first phase detector is a frequency synthesizer reference input, characterized in that output signal, serially connected counter, decryption The first 8 and second 9 controlled attenuators can be performed, for example, on p-i-n dioceses. The use of two phase detectors 2 and 3 makes it possible to eliminate the effects of the bias H; when i o, on the steady state frequency synthesizer. To reduce the level of interference at the output of a frequency synthesizer that is a multiple of frequency F, due to the finite reversal time of the control signal by the first 5 and second 6 phase shifters, two output frequency channels are used, alternately operating. The first of the channels includes the first GPN 12, the first controlled attenuator 8, the second phase shifter 6 and the first analog switch 10. The second channel contains the second GPN 13, the second controlled attenuator 9, the first phase shifter 5 and the second analog switch 1I. Moreover, the first 1 2 and the second 13 GPN can be implemented, for example, on the basis of an integrator with a reset. Consider the formation of the reference signals of the second 2 and third 3 phase detectors and commutas signal of frequency F enters the account in the form of binary channel. From generator 4 output chick 16, performed counter. The first and second bits of the counter 16 are connected to the input of the first and second bits of the decoder 17. The first, second and third outputs of the decoder 17 are respectively the outputs of its first, second and fourth bits. The signals from the outputs of the second and fourth bits of the decoder 7 are used as reference signals of the second 2 and third 3 phase detectors. In the first discharge of the decoder 17, a trigger control signal 18 is generated, which is turned on in the counting mode. On the first and second outputs of the trigger 18, which are respectively non-inverting and inverting outputs, form channel control signals, while  4T Oh Invention Formula A frequency synthesizer containing serially connected first and second phase detectors, a third phase detector, a frequency generator, a first phase shifter and a low-pass filter, and the first input of the first phase detector is a frequency synthesizer reference input, characterized in that output signal purity, a serially connected counter, a decoder, a trigger with a counting input, the first saw-tooth generator, the first controlled attenuator, the second phase switch the clamp and the first analog switch, the second sawtooth generator and the second controlled attenuator, the parallel adder, the inverting amplifier and the second analog switch, whose input is connected to the output of the first phase shifter, are connected in series with the output of the first analog switch and connected with the second input of the first phase detector, the output of which is connected to the input of an invertize tse amplifier, the output of which is connected to the first input of the third phase detector, The second input of the second phase detector and the second input of the third phase detector are connected respectively to the second and third outputs of the decoder, the outputs of the second and third phase detectors are connected to the corresponding inputs of the parallel adder, the output of which is connected to the input of the low-pass filter, the control input of the first controlled attenuator combined with the control input of the second controlled attenuator and connected to the output of the low-pass filter; the input of the second sawtooth generator is combined with a control The second input of the analog key is connected to the direct output of the trigger with a counting input, and the control input of the first analog key is connected to the inverse output of the trigger with a counting input, the output of the second controlled attenuator is connected to the control input of the first phase shifter whose signal input combined with the signal input of the second phase shifter and connected to the first input of the first phase detector, and the output of the frequency generator is connected to the input of the counter.