SU1314454A1 - Frequency synthesizer - Google Patents

Abstract

The invention relates to radio engineering. The purpose of the invention is to reduce the level of side components in the output signal spectrum. The synthesizer contains adjustable oscillators 1 and 9, a divider 2 frequencies with a fractional variable division factor, phase detectors (PD) 3 and 6, amplifiers 4 and 7 DC, filters 5, 8 and 11 low frequencies, totalizers 10 and 12 voltages and a reference generator 13. The goal is achieved by introducing PD 6, amplifier 7, filters 8 and 11, generator 9 and adders 10 and 12, with which the output of PD 3 is combined with an error signal and a signal that the phase of the output signal changes fragmentation signals an antiphase signal is generated fractional pensation signal by varying the phase shift of the signal generator 13. This voltage is, the impact on generator 1 sets the output signal and the side components from the interference compensated fractional. 1 il. (L and 4; SP 4

Description

The invention relates to radio engineering and can be used in radio receiving and radio transmitting devices and in measurement technology.

The purpose of the invention is to reduce the level of side components in the output signal spectrum.

The drawing shows an electrical structural diagram of a frequency synthesizer.

The frequency synthesizer contains the first adjustable oscillator 1, a divider, frequencies with fractional variable division factor (DCPD) 2, the first phase detector 3, the first amplifier 4 DC, the first filter 5 low frequencies, the second phase detector 6, the second amplifier 7 DC , the second low-pass filter 8, the second adjustable oscillator 9, the first adder 10 voltages, the third low pass filter 11, the second adder 12 voltages, the reference oscillator 13.

The frequency synthesizer works as follows.

The first tunable oscillator 1 is configured using an auto-tuning ring composed of a DDPD 2, a first phase detector 3, a first amplifier 4, and a first filter 5 ,, synchronized to the signal of the reference oscillator fg, and the frequency of the first tunable oscillator 1 is set to Nf 3 J where N is the division ratio of the DSPSP 2, the value of the phase difference between the input frequencies of the first phase detector is set around Ti / 2 due to the large gain value of the self-tuning ring. The video signal from the DDPC 2 video is fed to the reference input of the second phase detector 6, where it is compared in phase with the signal of the second adjustable oscillator 9 ,. The output of the second phase detector 6 produces a voltage error, which through the second amplifier 7 and the second (filter 8 leads the frequency of the second adjustable oscillator 9 to the frequency of the reference oscillation of the second phase detector 6. The phase of the output oscillation of the second adjustable oscillator 9 is due to The high gain in the feedback loop is 1G / 2 behind the phase of the reference signal.

five

0

five

Thus, the total phase shift between the oscillations of the reference generator 13 and the oscillations of the second adjustable oscillator 9 is

approximately ir. These signals, when summed in the first adder 10, are compensated with an accuracy to the constant component and high frequency components. The output voltage of the first adder 10 after filtering into

the third filter 11 folds down. reference signal. In the absence of interference, the fractionality resulting from the DDPD 2 operation, the voltage at the output, the third filter 11 is close to zero and the phase shift of the reference signal does not occur. In the presence of interference fragmentation, i.e. when N is not an integer and a sequence of pulses at the output of the DDPC 2 becomes either a non-periodic, or with a period equal to the fractional period, low-frequency discrete side components appear in the output signal spectrum of the DDPC 2. Due to the fact that the output of the DDPK 2 serves as a reference for the second phase detector 6, the output oscillation of the second adjustable oscillator also has non-periodicity. The restoration of the periodicity changes the polarity of the control voltage from the output of the second phase detector 11 and leads to the restoration of the periodicity to the oscillations of the second

5 by adjusting the generator 9. By selecting the inertia of the second filter 8, the optimum recovery time of the oscillation frequency of the second adjustable oscillator 9 is selected. When summing the oscillations in the first adder 10, the periodicity violation leads to a differential voltage. This voltage is summed up in the second summer 12 with the reference oscillation, changing the phase of the reference signal of the first phase detector 3 at times of periodicity violation according to a certain law S set by the second

0 and the third filters 8 and 11, and leading to maximum compensation of the fractional components of the output signal of the frequency synthesizer.

The required law of variation of the voltage 5 at the output of the second adder 12 is determined by the dynamic characteristics of the self-tuning ring of the first adjustable oscillator 1 and

3 13

the greater the inertia of the self-tuning ring, the more it is necessary to increase the inertia of the second and third filters 8 and 11.

At the output of the first phase detector 3, together with the error signal and the phase change signal of the DDPD 2 output signal, upon the occurrence of fragmentation signals, an antiphase compensation signal of fragmentation signals is produced by changing the phase shift of the reference generator signal 13. This voltage affects the first adjustable oscillator 1 , sets the output to be equal to the frequency N f, and the side components are canceled out due to interference.

Claims (1)

In this way, the side components in the spectrum of the output signal of the frequency synthesizer are reduced without increasing the inertia of the auto-tuning ring of the first adjustable oscillator 1 when receiving a fine frequency grid step. Invention Formula A frequency synthesizer containing a reference oscillator and connected Editor M. Dylyn Compiled by Y. Kovalev Tehred V. Kadar Proofreader M. Pojo Order 2219/55 Circulation 902 Subscription VNII1Sh State Committee of the USSR for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., 4/5 -Production and printing company, Uzhgorod, Projecto st., 4 54 4 the first adjustable oscillator, a frequency divider with a fractional variable division factor, a first phase detector, a first DC amplifier and a first low-pass filter, so that in order to reduce the level of components in the output spectrum, between the output of a frequency divider with a fractional variable division factor and a second input of the first phase detector are connected in series a second phase detector, a second dc amplifier, a second low pass filter, a second adjustable oscillator, a first voltage adder, a third low pass filter, and a second voltage adder , the second input of the first voltage adder is combined with the second input of the second sum — the voltage generator and connected to the output of the reference generator J, and the output of the second adjustable generator is connected to the second input of the second phase detector.