SU1280640A1 - Device for entering information from two-position transducers - Google Patents

Abstract

The invention relates to automation and computing and can be used in automated control and monitoring systems for entering information from two-position sensors. The purpose of the invention. is to increase the reliability of the input information. The device detects the addresses of the sensors that have changed their state and the time when the state of the sensor changes with the discreteness of the polling period. The device, as compared with the known ones, has a higher reliability of operation, which is achieved by the possibility of conducting a test mode without disconnecting two-position sensors from the network. The device generates a signal in case of exceeding its capacity and thus eliminates the possibility of receiving false information. This is achieved by introducing into the known device the third pulse generator, the second and third triggers, the first to fifth elements of AND, the third element - OR, additionally three control and one information inputs and one information output. 3 il.

Description

The invention relates to automation and computing and can be used in automated control and monitoring systems for entering information about the state of two-position sensors. The purpose of the invention is to increase the reliability of information input. FIG. 1 shows a structural diagram of the device proposed, FIG. 2 shows a timing diagram, explaining its operation, FIG. 3 — principle. Pial electric circuit of the third pulse generator. A device for inputting information from on-off sensors (FIG. 1) contains a generator 1 of a reference frequency, a second element AND 2, a first element OR 3, a divider 4 frequencies, a first driver 5 pulses, a second element OR 6, a second driver 7 pulses, a third element And 8, the third driver 9 impulses the fourth element And 10 ,, the first three ger 11, polling unit 12, five and 13, the second trigger 14, the shift pulse counter 15, the third trigger 16 register 17, the third element OR 18, the first element AND 19, counter 20 write pulses, a group of 21 elements OR, block The data 22, the first 23 and second 24 shift registers, the address encoder 25, the comparison element 26, the switch 27 and the request generator 28. The circuit also contains the inputs and outputs (29-40) of the device. Two information sensors are connected to the information inputs of the 34 groups (one sensor for each input). The number of sensors connected to one block 22 corresponds to the size of the second shift register 24. The size of the first 23 and second 24 shift registers is the same. The width of the address encoder 25 is determined by the number of blocks 22. The capacitance of the counter 15 shift pulses corresponds to the number of bits of the second shift register 24. The capacity of the counter 20 of write pulses corresponds to the maximum duration of the operating mode of the device. Control inputs 29-32 and control outputs 39 and 40 are designed to control the process of exchanging information between the proposed OS (the device and the data collection and processing device (not shown). Information on outputs 36-38 is used to remove information about sensors From the information outputs 37 of the first group, information is provided in the form of a parallel code and corresponds to the address of the sensor and block 22. From the information outputs 38 of the third group, the address of the block 22 is output in a parallel code, the bit of which corresponds to bit From the information outputs 36 of the second group in the parallel code, the sequence number of the recording pulse, which characterizes the response time of the sensor with the discreteness of the period of the recording pulses, is recorded. from the fourth information output, 35 reports the transfer of the capacity of the device. The recording pulses from the output of the second imager 7 arrive at a strictly defined frequency determined by for generators 1 and the reference frequency divider 4 frequency. A system consisting of I of the proposed device and a device for collecting and processing data has a certain bandwidth. Tie. It is designed to register a certain number of changes in the state of the sensors in one period of the following recording pulses. Information input 33 in test mode is supplied with test information in a sequential form, which is accompanied by clock pulses arriving at the second control input 30. The third control input 29 is designed to start the device into operation, a quarter control input 31 - to block the passage of recording pulses exit the third driver 9 on the second shift registers 24 in test mode. The second pulse shaper 7 is a one-shot that generates a pulse of a certain duration from the front of the input signal, and can be performed according to the scheme shown in FIG. The switch 27 is designed as a logic circuit that allows or prohibits the passage of multi-bit binary information depending on the control signal, and can be implemented on a group of two-input elements I. The basic electrical circuits of the first driver 5 of the polling unit 12 and the driver 28 are similar to the known ones . The device works as follows. The proposed device has a main and test modes. Before operation, the device is reset. To do this, the third control input 29 is given a signal that prohibits the pulse of the generator 1 of the reference frequency to the output of the second element I 2. Next, a signal is generated through a common reset circuit (not shown). At that, the divider 4 frequencies, the count of 20 write pulses, the first 11, the second 14 and the third 16 flip-flops and the first shift registers 23 of the blocks 22 are set to the zero state. A shift pulse counter 15 is set to overflow. The request formers 28 are set to the state corresponding to the absence of a request signal for their second outputs. The polling unit 12 is set to the state corresponding to the absence of a data signal Vyogod at its first output. The second shift registers 24 of the blocks 22 and the register 17 may be in an arbitrary state. The signal from the overflow output of the counter 15 pulses of shift through the first element OR 3 prohibits the first driver 5 to generate comparison pulses on its first output, and shift pulses on the second output. To provide the main mode of operation of the device at the second control input 30, there should be no clock pulses, at the fourth control input 31 there should be no signal prohibiting the passage of recording pulses to the output of the first element And 19, The third control input 29 is given a signal that permits the passage of pulses generator 1 reference frequency at the output of the second element And 2, After the filing of this signal through the time determined by the divider 4 frequency, the second driver 7 generates a write pulse. This pulse, in the absence of a prohibiting signal at the second input of the third element, And 8, is fed to the 404 input of the third former of the 9 pulses, which generates a signal of a certain duration. The write pulse from the output of the third driver 9 through the first element I 19 enters the second control inputs of the shift registers 24 of the blocks 22 n, records the current state of the sensors in them. After the information is recorded in the second shift registers 24, a comparison cycle begins. For this, a write pulse from the output of the third driver 9 restores the first driver 5 pulses to zero, sets the shift pulse counter 15 to zero, and the first 11 and third 16 triggers, resetting the first driver 5 means that after the pulse records are generated first by a Comparison Impulse, not a shear impulse. With a reset pulse reset to zero, the overflow signal is picked up at the first input of the first SHSh 3 element and a signal appears at its output allowing the first driver 5 to generate compare and shift pulses synchronously with the frequency of the reference generator 1. A comparison cycle begins in which there is a comparison of the contents of the first 23 and second 24 shift registers, the rewriting of information from the second shift registers 24 into the first 23, as well as the output of information in the case of incomparability. In each block 27. the comparison is carried out method on a one-bit bottom element 26 of the comparison. If the discharge bits are compared, then the next shift pulse is delayed and information is output, which is performed as follows. In block 22, in which incomparability occurred (incomparability can occur simultaneously in several blocks 22), the request generator 28 sets up a request signal at its second output, which through the second OR element .6 acts on the third input of the interrogator 12. The polling unit 12 in response to this action generates a signal to its first output, a data output, a polling pulse to the second output, and a polling signal to the third output with a delay relative to the pulse. Signal The output of data through the first element OR 3 prevents the first driver 5 from producing shift and comparison pulses. The polling pulse enters the sequential chain of drivers 28 for requesting blocks 22 and first meeting with driver 28 with the request signal set to switch to switch 27 of input channel 22, allowing information to pass through it. At the first output of this driver 28, a poll pulse no longer passes . Upon expiration of the polling pulse, the request signal at the second output of the imaging unit 28 is removed. Information from the switch 27 output through the OR elements of the group 21 is fed to the information inputs of the register 17. This information is written to the register 17 by the readiness signal, which also informs the data collection and processing device about the readiness of information at the information outputs 37 via the second control output 39 and 38 of the first and third groups, respectively. The first polling pulse generated in the comparison cycle is set to one first trigger 11. For a data acquisition and processing device, this means reading the counter of recording pulses 20 (only the leading edge of this signal is sensed) The data collecting and processing device reads the information from information outputs 37 and 38 of the first and third groups, provided that there is a corresponding signal from information outputs 36 of the second group, the signal goes through the first channeling yuschy input 32 to unit 12 poll. Moreover, if there is a request signal from the other blocks 22 at the third input of the polling unit 12, then it generates the next polling pulse, if there is no request signal, the polling unit 12 removes the data output signal at its first output and the first driver 5 starts producing shift pulses and comparison (as the comparison cycle continues, a shift pulse is generated first). After comparing the last bits of the shift registers 23 and 24, the shift pulse counter 15 generates a signal which, through the first element OR 3, prohibits the first driver 5 to generate comparison and shift pulses. Comparison cycle is over. The next comparison cycle occurs after the next recording pulse. During normal operation, i.e. in the absence of an excess of system capacity, the comparison cycle ends before the next write pulse arrives. If system bandwidth is exceeded, i.e. by the time of arrival of the next recording pulse, the comparison cycle is not completed, the new information about the current state of the sensors is not recorded, but the comparison cycle continues until the previously recorded information is completely processed, and the information output 35 shows a signal that the system capacity has been exceeded. This happens as follows. The second trigger 14 is set to the one state by the first comparison pulse, following the write pulse, and is reset to the zero state by the overflow signal coming from the counter 15 of the shift pulses, i.e. the finding of the second trigger 14 in the single state corresponds to the time of the comparison cycle. Thus, if the comparison cycle is not completed by the time of the arrival of the next write pulse, the signal from the inverse output of the second trigger 14 prohibits. the passage of the write pulse from the output of the second driver 7 to the output of the third element I 8, and the signal from the output of the second trigger 14 permits the passage of recording pulses through the third element 10 to the S input of the third trigger 16, setting it to one. The single state of the third trigger corresponds to the excess system capacity. This signal at information output 35 appears at the end of the action of the write pulse at the inverse of the input of the fifth element And 13. At the inputs of the third element And 8, the write pulse coincides with the signal from the second trigger 14 (finding the second trigger 14 in one state corresponds to cycle comparison). The duration of the comparison cycle depends on the timing of the information output. The information output is synchronized by the data acquisition and processing device. Consequently, a possible situation is when the second trigger changes its state during the action of the write pulse at the first input of the third element And 8, i.e. the comparison cycle ends at the time of the write pulse.

Consider the operation of the device in this situation (figure 2). Setting the second trigger 14 to a single state at the time of the recording pulse at the first input of the third element And 8 causes the recording pulse to be shorter than the input pulse at the output of the third element And 8. For the formation of a pulse, ensuring the stable operation of the device nodes, a third pulse shaper 9 is provided. The peculiarity of the third driver (Fig. 3) is that it generates a pulse of a certain duration from the leading edge of the input signal. In this situation, the third trigger 16 is set to one from the leading edge of the signal 5 coming from the output of the fourth element And 10, and then reset to the zero state from the leading edge of the write pulse from the output of the third driver 9 to its R input. As the third driver 9 flashes the write pulse, information is recorded in the second shift registers 24 and a new comparison cycle begins. Consequently, the signal from the switching of the third trigger 16 in this situation should not occur at the information output 35. For this, the recording pulse from the output of the second shaper 7, which delays the generation of the signal at the information output 35, is applied to the inverse input of the first element And 13. .

In order to ensure the test mode of the device, the third control input 29 is given a signal that prohibits the passage of a pulse from the generator 1 of the reference frequency to the output of the second element 2. The device is reset by the general reset circuit.

To the fourth control input 31; a signal is transmitted that prohibits the passage of recording pulses to the output of the first element AND 19. Information input 33 is sent in sequential form to the test information, which is accompanied by clock pulses entering the second control input 30. This is how the input test information in the shift registers 23 and 24 of the blocks 22. Then the third control input 29 is given a signal allowing the passage of pulses from the generator 1 of the reference frequency to the output of the second element II 2. After that, the device It makes comparisons of the information recorded in the shift registers 23 and 24 of the blocks 22, and performs data output in case of non-comparison of the bits. The comparison and output are performed in the same way as in the main operation mode.

In the test mode, both the number of inherent incomparisons and the order in which they are followed are monitored.

The implementation of the invention allows to increase the reliability of the information input device from the on-off sensors, which is achieved as follows.

The device provides the ability to conduct a test mode without disconnecting from the sensors. The test mode is based on the introduction to the shift registers through their successive inputs of test information. The nature of the test information can be very different, which allows one to detect not only stable residuals, but also failures that are random in nature.

Thus, alternating with a sequence of ones and zeros can be written into the shift registers, creating group switching of the bits of the shift registers at the maximum pulse repetition rate. I

The reliability of the device operation is also achieved by the exception of the possibility of generating false information in the event that the system capacity is exceeded, i.e. when the cycle. the comparison operation does not have time to end by the time of arrival of the next recording pulse. In this case, the device saves the previously recorded information and continues the comparison cycle until it is completely output, and a signal is generated that reports bandwidth exceeding. Formula and 3.0 device Device for inputting information from on-off sensors, containing a reference frequency generator, a write pulse counter, a shift pulse counter, first and second, pulse drivers, first and second elements OR, frequency divider register, first trigger, polling unit group of elements OR . and data generation units, each of which contains the first and second shift registers, the address coder, the reference element, the switch and the request generator, the first output of the first pulse generator is connected to the first inputs of the comparison elements of the data generation block, and the second output to the counter input of the shift pulse counter The outputs of which are the information outputs of the first group of the device, the output of the frequency divider is connected to the input of the second pulse shaper whose output is connected to the counting input of the counter Recording pulses, the outputs of which are information outputs of the second group of the device, the output of the first trigger is the first control output of the device, the first input of the first OR element is connected to the overflow output of the ssig pulse counter, the output to the first input of the first pulse shaper, the second input to the first output of the polling unit, the second output of which is connected to the S-input of the first trigger and the first input of the request generator of one data-generating unit, the third output - to the control input register a and is the second control output of the device, the first input of the interrogation unit is the first control input of the device, the second input is connected to the output of the second element OR the second input of the comparison element, the first input of the switch and the serial input of the first shift register 50

the second shift register, the third input of the comparison element and the second input of the switch are connected to the serial output of the first shift register, the output of the comparison element is connected to the second input of the request generator, the first input of the request generator of each AND block and the inverse input of the AND element are connected to the output of the second pulse generator, the second input of the third element And is connected to the inverse output of the second trigger, and the output is connected with the input of the third pulse generator, the second input of the first element And the fourth data source, besides the first one, is connected to the first output of the request generator of the previous data generation block, the second outputs of the requestors of the data generation block request are connected to the inputs of the second OR element, the third output of the request generator is connected to the control input of the switch, the address input which is connected to the output of the address encoder, the outputs of the register are information outputs of the third group of the device, the information inputs of the register are connected to the corresponding outputs of the Commodity OR groups whose inputs are connected to the corresponding information outputs of the switches of the data generating units, the parallel inputs of the second shift register are information inputs of the device group, characterized in that, in order to increase the reliability of the information input, the third pulse shaper, the second and the third trigger, five AND elements, the third OR element, the first input of which is the second M control input of the device, the second input is connected to the second output of the first one l pulses, the output of the third pulse generator is connected to the second input of the first pulse shaper, the input Set to zero the count of the shift pulses, the R-inputs of the first and third triggers and the first input of the first element AND, the output of the third element OR is connected to the control inputs of the first and the first control inputs of the second shift registers of the data generating unit, the first input of the second element I is the third control input of the device, the second input is connected to the output of the reference frequency generator, the output - to the input of the frequency divider, the third input of the first pulse shaper and third input interrogation unit, the first inputs of the third and fourth elemenII; i

the control input of the device, and the output is connected to the second control inputs BTOpbfx of the shift registers of the data fbration blocks, the S input of the second trigger is connected to the first output of the first pulse shaper, and the R input with the overflow output of the shift pulse counter, the forward output is with the second input of the fourth element And, the output of which

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connected to the S-code of the third trigger, the output of which is connected to the direct input of the fifth element I, the output of which is the informational 2 output of the device, the combined serial inputs of the second shift registers of the data generation units are the information input of the device 10.

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Claims (2)

Claim' A device for inputting information from on-off sensors, comprising a reference frequency generator,. 5 write pulse counter, shift pulse counter, first and second, pulse shapers, first and second OR elements, frequency divider, register, first trigger, polling unit, 0 group of OR elements. and data generating units, each of which contains the first and second shift registers, an address encoder, a comparison element, a switch and a request generator 15, the first output of the first pulse former is connected to the first inputs of the comparison elements of the data generation units, and the second output to the counted input of the pulse counter 20 of the shift, the outputs of which are the information outputs of the first group of the device, the output of the frequency divider is connected to the input of the second pulse shaper? whose output is connected to ^{2 May} chen count input a write pulse counter whose data outputs are the outputs of the second device group, the first latch output is the first control output of the apparatus 30, the first input of the first OR gate connected to the output shift pulse counter overflows, the output - to the first the input of the first pulse shaper, the second 35 input to the first output of the polling unit, the second output of which is connected to the S-input of the first trigger and the first input of the request shaper of one forming unit data, the third output is with the control input of the register and is the second control output of the device, the first input of the polling unit is the first control input of the device, the second input is connected to the output of the second OR element, the second input of the comparison element, the first input of the switch and the serial input of the first shift register is connected to the serial output of the second shift register, the third input of the comparison element and the second input of the switch are connected to the serial output of the first shift register, the output comparison element 55 is connected to the second input of the query generator, the first input of the query driver of each data generation unit, except the first, is connected to the first output of the query former of the previous data generation unit, the second outputs of the query former of the data generation unit ^ are connected to the inputs of the second OR element , the third output of the query generator is connected to the control input of the switch, the address input of which is connected to the output of the address encoder, the outputs of the register are information outputs and the third group of the device, the information inputs of the register are connected to the corresponding outputs of the OR elements of the group, the inputs of which are connected to the corresponding information outputs of the switches of the data generation units, the parallel inputs of the second shift register are the information inputs of the group of the device, characterized in that, in order to increase the accuracy of the input of information , the third pulse shaper, the second and third triggers, the five AND elements, the third OR element, the first input of which is are the second control input of the device, the second input is connected to the second output of the first pulse shaper, the output of the third pulse shaper is connected to the second input of the first pulse shaper, the input Set the shift pulse counter to zero, the R-inputs of the first and third triggers and the first input of the first element And, the output of the third OR element is connected to the control inputs of the first and first control inputs of the second shift registers of the data generation unit, the first input of the second AND element is the third with a directing input of the device, the second input is connected to the output of the reference frequency generator, the output is connected to the input of the frequency divider, the third input of the first pulse shaper and the third input of the polling unit, the first inputs of the third and fourth elements And the inverse input of the element And are connected to the output of the second pulse shaper, the second input of the third element And is connected to the inverse output of the second trigger, and the output is connected to the input of the third pulse shaper, the second input of the first element And is the fourth n: 1280640 connected to the S-input third flip-flop, whose output is connected to the direct input of the fifth AND gate, the output of which is an information 5 by the device output, combined by the control input of the device, and the output is connected to the second control inputs of the second shift registers of the data framing units, the S-input of the second trigger is connected to the first output of the first pulse shaper, and the R-input is connected to the overflow output of the shift pulse counter, direct output - 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