RU1785087C - Reserved system - Google Patents

Description

The invention relates to the field of computer engineering and can be used in engineering

computing systems and devices of increased reliability and performance.

The purpose of the invention is to increase system performance by operating in synchronous and asynchronous mode.

In FIG. 1 shows a functional diagram of a redundant system; in FIG. 2 - priority permission block; in FIG. 3 is an embodiment of a microprocessor unit; in FIG. 4 - arbitration scheme; in FIG. 5 is an embodiment of a control unit; Fig. 6 - control unit; in FIG. 7 - restoring authority to the first category of information; in FIG. 8 input / output units.

A redundant system (Fig. Consists of three redundancy channels, each of which includes a synchronous computing device 1, the first 2 and second 4 bus drivers, control unit 5, input-output unit 10, asynchronous

a computing device consisting of a control unit b, a memory unit 7, a microprocessor unit 8, a priority resolution unit 9, the System also contains a recovery unit 3 common to the reserved channels.

In FIG. 1, interrupt input 11, access output 12, ready input 13, information input-output 14, command output 15 of the synchronous computing device 1, bus 16, system data bus 17, system address bus and command 18.

Priority resolution block 9 - FIG. 2, consists of a counter 19, a two-input OR element with an open collector 20, an inverter 21, a first three-input element NAND 22, a second three-input element NAND with an open collector 23

Microprocessor unit 8 - FIG. 3, contains a generator 24, a microprocessor 25, bus controllers 26, 27, registers 28, 29 bus drivers 30, 31, program C.W

adjustable counter interrupt 32, wake-up memory 33, inverters 34-39, open collector element 40, I 41 elements, NAND 42,43, decoder 44, bus arbiter The arbitration scheme - Fig. 4, shows bus arbiters 45 computing devices and microprocessor units 8 in connection with priority resolution blocks 9 sin of asynchronous computing devices,

Control unit 5 - Fig. 5, consists of comparison circuits 46, 47, I-HC elements 4B, 49, trigger 50, element NOT with open collector 51, decoder 52, former 53, register 54 with the third state, input 55 logical unit.

Control unit 6 - FIG. 6, register register 56 decoder 57, inverter ri8, multiplexer 59, inverter 60.

The restoring organ 3 - Fig 7, is built on the elements of disambiguation 61-63 and the majority elements 6l-66

The input-output block 10 - Fig. 8, consists of a bi-directional bus driver 67, a decoder 68 and a programmable parallel interface 69

Synchronous computing devices 1 can be constructed according to the scheme of microprocessor units 8 shown from FIG. 3.

In Fig. 1, the outputs of the interruption of control units 5 of the redundancy channels are connected to the interrupt modes of 11 all synchronous computing devices 1; access output 12 and ready input 13 of the synchronous computing device 1 of each backup channel are connected to the input of the same name as the output of the asynchronous computing device ( inputs of the same name, outputs of priority block 9, microprocessor block 8) Information input-output 14 of device 1 is connected to the simultaneous output-input of the first bus driver 2, present This is an n-bit data source. The output of commands 15 of device 1 is connected to the control input of the first bus driver 2, the information input of the first group of inputs of the restoring organ 3, the first information input of control unit 5 at the output of commands 15 by synchronous computing device 1, a set of control signals m-bit address The output of the asynchronous computing device in each channel is also a bus 16, to which an access permission input is connected to the arbitrator bus 45 of block m processor 8, input element 22 and output of element 20 of priority permission block 9. Bus occupied output of the bus of the asynchronous computing device of each reservation channel is connected via the corresponding bus 16 to the inputs of the same asynchronous computing devices of the remaining channels - to the corresponding inputs of the samples 22 of blocks 9 ( FIG. 4) Information input-output of the second bus driver 4 is connected to the same output-input of the unit

0 zyoda-zvoda 10, asynchronous computing device (control unit 6, amty 7, microprocessor 8) through this dark data bus 17. The information output of the second group of outputs of the recovering organ 3 is connected to the control inputs of the second bus driver 4, asynchronous computing device - control units 6, memory 7, microprocessor 8, control unit 5, input-output unit 10 via the system bus of the bit address and commands 18. The recovery control output of device 1 (Olok's first output 6) is connected to the corresponding the same login

5 re-instilled body 3, the output of the control unit 5 exchange (from trigger 50) - to the inputs of the control units of the same name 5 of the remaining backup units, the information output of the first group of outputs

0 part of this body 3 - to the information inputs of the first bus drivers 2 and the second information inputs of the second bus drivers A and control block 3 of the corresponding reservation channels 5

The system operates as follows: 1 p 11 si nn n n 11 output and data input devices 1 (FIGS. 1, 3) process data on the same programs stored in

0 local DIRECTIONS 33 and (or) block 7 of asynchronous computing devices, Synchronous exchange of information between microprocessors 25 of devices 1 and memory blocks 7 is carried out through a recovery member 3, which performs a majority function with the signals arriving at its inputs.

8 mode of writing (or reading) data to the memory (from the memory) of the address bus and commands

0 J5 through the reducing body 3 are connected to the system buses 18 which are connected to the address and command buses of the blocks 7. When writing data from the microprocessors 25 of the device 1 via the bus 14,

5 bus drivers 2 restoring body 3, bus drivers 4, system buses 17 are fed to the input of memory blocks 1. When reading, the data transfer direction is reverse. Switching control bus formers 2, 4

carried out by control signals from buses 15, 18, Similarly, synchronized data exchange of device 1 with input / output units 10 is carried out.

Synchronous computing device 1 also has the ability to read data from only one memory unit 7 (in three channels). In this case, when accessing to a specific memory address, the control units b generate at their first outputs single signals that are fed to the corresponding control inputs of the reducing body 3. When applying to the control inputs of the recovering body from two control units (in two channels) of single signals, at its output there is a signal from the input to which unit 7 of the third channel is connected.

Microprocessor units 8 of asynchronous computing devices operate in each channel asynchronously according to their own programs, which are also stored in their local memory 33 and (or) blocks 7. Moreover, the microprocessor 25 of block 8 has the ability to access only its own memory block 7 channel through the buses 17, 18. Therefore, the failure of any block 8 deactivates only one system bus or memory area in blocks 7.

The time distribution of the total resources of the system (buses 17, 18. of blocks 7) is carried out using priority resolution blocks 9 and arbiters 45 (Figs. 1-4). The operation of microprocessors of computing devices with a common memory - blocks 7, can be organized by known methods for multiprocessing - through a semaphore or mail box (arbitration - serial).

Consider one of the possible options for multiprocessing information processing.

Let the task be to collect data from two external devices (three-channel), process data from each device according to a certain algorithm in the output of results to external devices.

Algorithms for solving the problem can be distributed between microprocessors as follows.

The microprocessors 25 of the devices 1 synchronously collect data from external devices via blocks 10 through three channels, process data from one of the external devices according to the first algorithm, and place data from the second external device into memory blocks 7 for blocks 8 of the first and second channels.

The processing of data from a second external device is performed by microprocessors of 25 units according to the first algorithm. The processing results of blocks 8 are placed in certain memory zones of blocks 7. Synchronous devices 1 compare the results of data processing using the second algorithm and transmit them, if they are identical, to the external devices via input / output blocks 10. The results of data processing according to the first algorithm are also synchronous computing devices 1 to external devices.

The microprocessor 25 of the third channel unit 8 may be in reserve. If the processing results in blocks 8 are not comparable and the channel is identified with a faulty microprocessor, the operating system should redistribute the task between blocks 8.

The highest system performance can be achieved by solving problems for which the data processing time using memory is significantly longer than the time the microprocessors access shared resources.

Data exchange between microprocessors 25 of synchronous and asynchronous computing devices can be carried out either using special prefixes and commands to analyze signs of updating information in the corresponding memory cells, or by requesting interruption of programs.

In the second case, devices 1 placed in processing units 7 can generate interrupt requests into each of units 8 (for example, via a software-accessible trigger — not shown in FIG. 3). For these processes, blocks 8 in the corresponding interrupt processing programs select the necessary information from blocks 7. On completion of processing, blocks 8 can also inform devices 1 by appropriate requests.

Coordination of microprocessor access to system buses is carried out as follows (Figs. 1-4).

The priority access permission access to the BPRO bus of the arbiter 45 of each device 1 (bus 12) is connected to the priority access extension of the access to the BPRN bus of the arbiter 45 of block 8. If the microprocessors of 25 devices 1 do not use the system bus, the arbiters 45 of devices 1 synchronously transmit the priority to the arbiters 45 of blocks 8 - zero BPRO signals, If devices 1 capture the bus, then single signals simultaneously appear on the BPRO outputs (The priority access permission input to the BPRN bus of devices 1 is permanently connected to logical zero, ensuring that m, these blocks Cat highest priority), When capturing system bus devices 1 or blocks 8 at respective tires on busy BUSY are zero signals which are removed upon release of the system

TIRES.

In the initial state, when devices 1 and blocks 8 do not access the memory blocks 7, zero levels are set at the inputs for accessing the BPRN bus of the arbiters 45, accommodating the access to the system buses 17, 18 (AS arbitrators operate in the mode in which the bus after each access to it, the input ANIRQS-log I, CBRQ. О,),

Zero BPRO signals, these are 19 blocks 9 and the original state (logical zero at the output), Busbars of BUSY arbiters 45, there are logic unit signals at the outputs of elements 20, 33, indicating that the system buses are free

If the microprocessors of device 1 are the first to grow on the system buses, then at the outputs of the BPRO arbiters 45, single signals appear simultaneously in three channels, preventing block 8 from accessing the buses. The counters 19 of the blocks 9 begin counting the pulses of frequency f which can be supplied to the blocks 9 from individual milli generators from the BCLK buses of the microprocessor blocks. The division coefficient of the counters is selected so that a single signal appears at their outputs after a time longer than the maximum time the block @ 8 can access the system buses. Since blocks 8 did not access the buses, a zero signal is generated at the output of element 22, and a single signal is generated at element 23, which is fed to the input of BUSY arbiters 45 of devices 1. By analyzing a single signal level at the output of BUSY, arbiters 45 allow devices 1 to access the system buses If the system bus was occupied by blocks 8, then at the output of element 22, the zero signal only occurs after the BUSY signal is set to the arbi- tra 45 of the corresponding block 8 (bus 16).

In the event of a failure in any of the blocks 8, when there is a constant unit level at the output of element 22, a single signal from the output of element 23 appears at the input of BUSY arbitrators 45 of devices 1 only at the end of the calculation of element 19. In such failures, the system performance will be reduced since device 1

“Always turn on the system buses with a delay for the generation of a single signal with“ encoder 19. Resetting of the counter 39 occurs but the BPRO level is zero for every device I accessing system shiism

During the capture of buses by devices 1, the corresponding referees 45 ayat zero busy signals - SUSY, which are held until the end of the call, Pr 8 PRO in devices 1 is zero (until the BUSY signal is removed), the zero level through element 20 is connected to the input

BUSY arbitrators 45 blocks 8, prohibiting block- KSM 8 appeal,

Blocks at a zero signal at the BPRN inputs to the system buses are accessed by blocks I do not exit the output of the bus

of block 8, a zero level is sent before the end of the call. This CHI channel through the elements 22, 23 informs the arbiters 45 of the devices 1 about the bus occupancy when switching the signal RPRO of the arbiters 15 of the devices

per unit.

1 malfunctions were detected in the major r-rrvirooange / 1 with the OSU and lstvllat system blocks similarly to the prototype from control blocks 5.

in blocks 5 (Fig. 5}, in the case of Absence of non-inaccurate trigger 50 is triggered into condition (by RESET signal) At elements b, 47, bitwise comparison of signals from data buses, addresses, /

control the output of the regenerating organ 3 with signals on the tins 15 and the outputs of the bus X of the microchromes 2, 4. The mismatch of the signals is stored in the trigger 50, the output of which is through an inverter open

a collector 51 is connected to the outputs of the shapers 53 of all channels, cut out) - U1Co1x the write pulse to the registers 54. The DURATION of the pulse is determined by the RiC chain, in case of disconnection of the correct channels or operation of three devices 1 with one unit 7 (in read mode) with from the first outputs of blocks 6, the outputs of the elements 49 must be supplied with single signals of the bottom of the blocking of the trigger BB.

In registers 54, information is stored at the same time that characterizes the channel number and the status of the majority tins, for example: control hygiene (entries in the MWTC memory, read and memory MRDC, etc.), addresses, data

The signal from the combined OUTPUTS of the electric S1 will also be sent to the breaker bus in §n 1 11 synchronous computing

devices 1. Having received this signal, devices 1 interrogate the registers 54 through the restoring authority 3, bus drivers 2, 4 and process the received information. The bit depth of the registers 54 depends on the required depth of fault diagnosis.

From the contents of register 54 (the values of the signals recorded in it), it is possible to determine the type of faulty unit. Fixation in the registers 54 of the control signal record (code in bits D4-D6-SI1) or read (code III) indicates the appeal of devices 1 to blocks 7; latching of the control signal, the IOWC output (code 110) or IORS input (code 101) indicates the access of units 1 to blocks 10. If the signals read or input are fixed in the DZ bit, a logical zero, i.e. there was a mismatch on the data buses, then the faulty block is 7 or 10. Fig. 5 shows the connection to the DZ bit of the output register 54 of the element 47 to determine the mismatch in the data buses of only one channel, for example, the first. If the logical unit is in the DZ bit when reading or entering data, then device 1 is faulty. Fixation in the DO-D2 bits of the NO code corresponds to a fault in the first channel, OIO code in the second channel, 00 in the third channel.

By bit D7, it is possible to determine the area of memory in which a malfunction is recorded. The address of the register is determined by the descrambler 52. Reset of the trigger 50 - by polling the register 54.

Faults in asynchronous computing devices must be determined programmatically: by comparing the results from different channels,

The devices 1 write information to the registers 56 through the elements 2,3,4, which determines the state of the outputs of the control units. The bit Qo of register 56 determines the state of the second output. A logical unit written in this category disables the output buses of the corresponding microprocessor unit 8. Such a shutdown is performed when a failure is detected in units 8 (by software comparison of results, testing, etc.).

The logical unit recorded in the QI bit of the register 56 through the multiplexer 59 and the first output of the control unit is fed to the control input of the recovering organ 3 when data is read by blocks 1 from one memory block 7: from the zone defined by code 00 to bit address address A18, A19 of the system bus 18. Supply of a logical unit to the inputs of the restoring organ

3 in two channels transmits signals to the output of the reducing organ from the third channel. With the synchronous operation of three devices 1 with three memory blocks 7 at addresses with a high order value A19, A18 equal to 00, and failure detection in one of the blocks 7, it is possible to switch the recovering organ 3 to work from one working channel in data reading mode .

Devices 1, blocks 8 can access the entire memory area of blocks 7. 8 at the same time, the memory zones intended for sharing are determined by the high order bits of the address A19, A18 of the buses 18. Moreover, each block 8 has its own area. disjoint with other areas of blocks 8. Devices 1 record data simultaneously at the same address in three blocks 7, for three blocks 8 in three calls. Data reading by three devices 1 from one unit 7 is performed when single signals from the outputs of multiplexers 59 of control units 6 are supplied to the corresponding inputs of the reducing organ 3.

In FIG. 6 shows the supply of the software code multiplexer 59 to the DZD-D1 bit, which corresponds to the appearance of a single signal at the first output of block 6 with a code in bits A19, A18 equal to 11 or 10. In the second channel, the IOI code must be supplied, in the third - HE.

Block 8 of the first channel must exchange data with devices 1 through a memory area with a code in bits A19, A18-01. For this code, the logical units appear at the outputs of blocks 6 of the second and third channels when reading data from devices 1. Accordingly, block 8 of the second channel must communicate with device 1 through the memory area with the code in A19, A18-10, block 8 of the third channel - through the memory area with the code in A19, A18 - I.

A specific code at the information inputs of multiplexer 59 can be set constantly (wiring) or through register 56.

Selective writing to the registers 56 is done from the corresponding outputs of the decoder 57 (at different addresses); DLC of the first channel - from output 1, the second - from output 2, the third - from output 3.

In FIG. 7 is a diagram of a reducing organ 3 per one bit of information. Majority elements 64-65 perform a majority function on input signals. Disambiguation elements 61-63 invert input information when received on

control input of single logic levels, or repeat information at zero signals at control inputs,

Devices 1, blocks 8 (Fig. 3) are constructed according to a typical scheme for a microprocessor kit of the K1810 series. Microprocessors 25 operate at maximum speed, Generator 24 can operate from its own quartz resonator G (for units 8) or from an external redundant generator at the EFI input (for devices 1). The generator generates control signals RESET, READI for the microprocessor, as well as the clock frequency CLK, BCLK.

The control system signals are generated by the bus controller 27, and the resident ones by the controller 26, the system address is latched in register 29 and the resident address into the register 28. System data is generated by the bus drivers 31.8 resident by the bus drivers 30.

Arbitrator 45 operates in configuration mode with a system and resident bus. The bus is selected using the address decoder 44.

A local memory 33 and a programmable interrupt controller 32 are installed on the resident bus. For example, the diagram shows only one INTI interrupt request, which can be used as a request from control unit 5,

Arbitrator 45 operates in a mode where the system bus is released after each access (CBRQ signal is connected to logic zero. In synchronous computing devices 1, the BPRM input of arbiter 45 must also be connected to logic zero permanently, thereby providing the device with the highest priority.

Arbitrators 45, controllers 26, 27 operate according to the state of the SO-S2 buses of the microprocessor 25. The output buses of block 8 are blocked from block 6 by the signal supplied to the inputs of elements 41-43.

The I / O block (Fig. 8} using a programmable parallel interface - element 69 can exchange data with external devices through three programmable ports A, B, C. The element 69 is accessed by signals from the system buses 17.18 through two - directional bus driver 67 and decoder 68.

Claims (1)

The claims A redundant system containing a reducing organ, and in each redundancy channel, a synchronous computing device and a control unit, and in each redundancy channel, the command output of the synchronous computing device is connected to the first the information input of the control unit and the corresponding information input of the first group of inputs of the recovering organ, the corresponding information output of the first group of which is connected to the second input of the commands of the control unit, the exchange output of which is connected to the same inputs of the control units of the remaining reservation channels, and the interrupt outputs of the control units 5 of all redundancy channels are connected to interrupt inputs of all synchronous computing devices, characterized in that, in order to increase system performance due to operation in synchronous and asynchronous modes, an asynchronous computing device, an input-output unit and the first and the second bus formate, and in each channel 5 of the reservation, the information input-output of the synchronous computing device is connected to the same output-input of the first bus driver, to the control input of which there is a key output of the synchronous computing device commands, and the information output is connected to the corresponding information input of the second group of inputs of the recovering organ, to the first information the inputs of the cantrop unit and the information outputs of the second bus driver of their backup channel, the information outputs of the first group vosstanavlivzyusche0 th body information outputs connected to first inputs of the bus drivers and the second data inputs of second bus drivers and the respective channel control units reservation, 5 9 of which the outputs of asynchronous computing devices are connected to the same inputs of asynchronous computing devices of the remaining redundancy channels, in each redundancy channel the information input-output of the second bus driver is connected to the same outputs-inputs of the I / O unit, asynchronous computing device and control unit, access output 5 and the readiness input of the synchronous computing device are respectively connected to the output and input of the asynchronous computing device of the same name, the recovery control output of which is connected to the corresponding input of the recovery organ-bus former, asynchronous output, the corresponding information computing device, control unit, and the course of the second group of outputs of which the input / output block of its channel is reserved is connected to the control inputs of the second theft. ШШ Fi2 Hask Network) FIG. 5 R & la schkra & lsu Swopou ttJfod