SU1265990A2 - Switching device - Google Patents

Abstract

The invention relates to an electrical measuring tehpike and can be used in a switch. Measure it. Ti-information 1x systems. The goal is to expand the functionality of the switch. D.1 of this in a multi-channel switch on aut. St. No. 1182658 additionally introduced1 1 two units of comparison, unit stat. | numerical measurements, counter, trigger, two y.ieMoiiTa OR, format 11.11s and o.chok.Lenret. In ycTpoiicTBC, it is possible to determine the speed, .bi. lag time synchrohimglso fires for clock pulses .i.ui each. cana ta individual, in view of its b1) 1stro action and in a wide time range. automatic ix perekio.iocheeie. This is the possibility of using comm | ts of 1 pc with individual tins of t.1 of tron1) 1x keys, the possibility of operating.-ibHoio number.1a measurements on the short circuit Kana.ie with the first and the pic, 1duk) P1 of ii3 Kpeiiiiii. 1H) provides many measurements on a capacitor. With MaKcima.ihHoii, the polling rate is 1 °. 1 il.

Description

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NJ The invention relates to electrical measuring equipment, in particular, to switches of measuring information systems, and is an improvement of the known device according to the author. St. No. 1182658. The purpose of the invention is to expand the functionality by providing an arbitrary number of measurements on a closed channel with regard to the first and subsequent measurements. The drawing shows the functional diagram of the switch. The switch contains P switching blocks 1.1-1.1P, consisting of M switchboards 2.1-2.M switching input measurement signals, which are connected to the output of a group of N channels, trigger 3 work resolution, connected in series specifying high-frequency generator 4, divider 5, a switching device 6, serially connected counters 7-9, a decoder 10 / V channels, a decoder 11 M channel groups, a decoder 12.P switching units, the outputs of the decoders are connected to the control inputs of the corresponding L channel s M channel groups P switching units. M controllable formers 13.1-13.M by the number P of switching units, two counters 14 and 15, two blocks 16 and 17 of comparison, three elements OR 18-20, two triggers 21 and 22, block 23 of settings for polling rate, block 24 settings for pause. block 25 of the polling rate settings, block 26 of the settings,. pause values, block 27 of the address settings of the switching time parameters, two registers 28 and 29, two additional controlled shaper 30 and 31, block 32 of the settings of the delay time of the clock pulses, inverter 33, two elements And 34 and 35, Start 36 and Reset buses 37, "Sync pulse 38," Fixed speed 39, data bus 40, bus 41 addresses. the third 42 and fourth 43 blocks of comparison. block 44 of the settings for the number of measurements, the third counter 45, the third trigger 46, the fourth 47 and the fifth 48 OR elements, the driver 49, the prohibition block 50, the bus "End of operation 51," Continuous polling 52. At the same time, the output of the switching device 6 is connected to the counting the input of the first counter 14, the output of which is connected to the first inputs of the first comparison unit 16, the second inputs of which are connected to the combined outputs of the polling rate settings block 25 and the pause size settings block 26, the output of the first comparison block 16 is connected to the first inputs of the first 18 and 19 OR elements, the second inputs of the OR elements 18 and 19 are connected to the Start 36 and Reset 37 tires, respectively, the outputs of the OR elements 18 and 19 are connected to the counting input of the first trigger 21 and the installation inputs of the dividers 5 and the first counter 14, respectively, by output the first trigger 21 is connected to a counting input of a 7 / V channel counter, gating inputs of decoders 10–12 L channels, M channel groups, R switching units, to a counting input of a second trigger 22, and to counting inputs of block 23 of the order of the polling rate and block 25 charter to the magnitude of the polling speed, the inverse output of the first trigger 21 is connected to the read inputs of the set 24 of the pause order and the pause setting block 26, the combined outputs of the set of the polling speed 23 and the set 24 of the pause order are connected to the address inputs of the switching device 6 , the outputs of the counters 7-9 N channels, M groups of channels, R switching units are connected to the address inputs of the block 32 of the delay time settings for clock pulses and with the address inputs of the block 27 of the settings of the address of the switching time parameters, output connected to the outputs of the first 28 and second 29 registers and to address inputs of setting blocks of order 23 and polling rate of 25, blocks of settings of order 24 and pausing 26, reading inputs of blocks of address setting of switching time parameters 27 and delay time of sync pulses 32 connected to the output of the trigger 3 enable work and the installation input of the first trigger 21, the inputs M of the controlled drivers 13.1-13. M in each switching unit P are connected to the outputs of the type of switchboard corresponding M switchboards control boards, with the outputs of the 11 M channel descrambler channel groups, and the combined outputs with the control input of the first additional control driver 30, input of the inverter 33, first input of the second element I 35, output of the inverter 33 connected to the first input of the first element Both 34 and the control input of the second additional control driver 31, the combined second inputs of the first 34 and second 35 elements And are connected to the bus 39 "Fixed speed, the output of the first element And 34 is connected to the control input of the first re the horn 28, the output of the second element I 35 is connected to the control input of the second register 29, the inputs of the first 30 and second 31 additional controlled drivers are connected to the outputs of dividers 5, and the combined outputs to the counting input of the second counter 15, the output of which is connected to the first inputs the second comparison block 17, the second inputs of which are connected to the output of the block 32 of the delay pulse timing settings, and the output to the installation input of the second trigger 22 and the second input of the third element OR 20, the first input of which is connected to the bus 37 "Reset, and the output - with the installation input of the second counter 15, the output of the second trigger 22 is connected to the bus 38" Clock, the data inputs of the six blocks 23-27 and 32 settings are connected to the data bus 40, the address inputs of the two registers 28 and 29 are connected to bus 41 addresses.

In addition, the first inputs of the first b.yuk 16 comparison and the output of the first counter 14 are connected to the first inputs of the third comparison block 42, the second inputs of which are connected to the second 1 input of the first comparison block 16 and to the combined outputs of the Iauza value setting 26 and block 25 the settings of the polling rate, the read input of the latter is connected to the read input of the block 23, the order of the polling speed, the counting input of the 7 L channel counter, the gating inputs of the depot 10-12 .V channels, M channel groups, P switching units, counting input the house of the second trigger 22, the direct output of the first trigger 21 and the control input of the third comparison unit 42, the output of which is connected to the input of the driver 49 and the counting input of the third counter 45, the output of which is connected to the second inputs of the fourth comparison block 43, the first inputs of the last one with the output of the block 44 of the settings for the number of measurements, the address inputs of which are connected to the address inputs of the block 32 of the clock delay settings, block 27 of the address settings of the switching time parameters and the outputs of counters 7-9 .V channels, M g A channel of channels, P switching units, and data inputs are connected to data bus 40, the output of the fourth comparison unit 43 is connected to the first input of the fifth element OR 48 and the second installation input of the third trigger 46, the first installation 1 of which is connected to the B151 input of the second trigger 22, 38 "Sync pulse and the first input of the fourth element OR 47, the second input of which is connected to the output of the imaging unit 49, and the output - with the bus 51" End of operation, the output of the third trigger 46 is connected to the first input of the prohibition unit 50, the second input of which is connected to the bus 52 "Nepra yvny survey, and an output - to a second input of the first mounting latch 21. The second input of the fifth OR gate 48 is connected to the bus 37 'Reset, and output - with ustanovochny.m input of the third counter 45.

The switch works as follows.

Before starting work, the corresponding data from UJHHBI 40 data is recorded into blocks 23-27, 32, and 44 remotely or from controls. The setting by sending a signal "Reset on bus 37 through OR 19, 20 and 48 elements is set to zero state the counters 14, 15 and 45, the trigger 22, and the trigger 3 are in a state that prohibits the operation of the switch, i.e., the operation of the trigger 21 is blocked.

On the "Start-up bus 36" signal, the work enable trigger 3 is set to the state allowing clock pulses to the counting input of the counter 7. The "Start-up signal through the OR 18 element sets the trigger 21 to the state in which the forward output appears the pulse whose leading edge is the leading edge of the first clock pulse, and the counter 7 arriving at the counting input, thereby setting the counters 79 to the state corresponding to the first channel in the cycle. From the output of counters 7--9, the code of the number of the first channel goes to the inputs of the decoders 10-12, from the output of which the signals come to the BXCXTI I corresponding to R b, forged 1.1 to 1. P commutation, L switchboard 2.1-2. . and.-Y channels, and pro: 1 The first channel closes. The code from the outputs of counters 7-9 postunag on address inputs b, choke 27 settings, and the pulse from trigger 3 permits reading the contents of the corresponding memory on B1) 1 input of unit 27 ycTaiiOK and one (time 11Н () to address input 1) 1 b, 1 23 2 (i settings, thereby forming the address of the memory cells. A parameter is stored in KOTOpiiix) 1 KONI switching of the first channel. The impulse from the direct output of the trigger 21 allows the reading of the contents of the memory cells in the bays 23 and 25 of the setpoints, which determines the order and length of the channel polling rate but the frequency. defined by B1) with a block input of 27 shifts. The code for the polling rate from the output of the setpoint block 23 is sent to the addresses of the input of the switching device 6, thereby passing the counter 14 pulse to the counting input from the corresponding outputs de, 1G1 5, which are 1a4 from the high-frequency generator 1a 4 a given number of times . The code from the output of the counter 14 is transferred to the first inputs of block 1 in the comparison, and the second inputs of which have the code of the magnitude of the polling rate from the output of block 25 of settings. Pr11 coincidence of impu codes. from the output of the comparator unit 16 through elements OR 18 enters the counting input of flip-flop 21, sets it to a state in which the signal from the 1st output allows the reading of the contents of memory cells in b, yuki 24 and 26 settings, which is specified and the value of the pause at the address, on the output of the output b, 1 of the 27 settings, and the reading of the blocks J. goes down.

Simultaneously imiu.tis from the output of the comparison block 16 through e, 1 or OR 19 sets the divide 1 to the zero state.1 and 5 and the counter 14. The code for the order of pauses from the output b, 1 about 24 settings goes to the address input of the non-switching device 6, thereby resolving passing through the counting input of the counter 14 pulses from the corresponding outputs of the dividers 5. The code from B1 of the input of the counter 14 enters the first inputs of the comparison block 16, the second inputs of which have a pause value code e of the output block 26 of the settings. Iri match imiu codes, 1s with exit

the comparison unit 16 through the element OR 18 enters the counting input of the trigger 21, sets it to a state in which the signal from the direct output allows reading the contents of the memory cells in the setting blocks 23 and 25, and the leading edge of which is the leading edge of the second a clock pulse arriving at the input of the counter 7. At the same time, the pulse from the output of the comparison unit 16 through the OR element 19 sets the dividers 5 and the counter 14 to the zero state.

Thus, the formation of the first clock pulse, the duration of which consists of the magnitude of the speed of the survey of the first channel and the pause between the opening of the first channel and the closure of the second. The leading edge of the second clock pulse at the counting input of counter 7 changes its state by +1, which causes the next channel to close and the memory cell address in the setting block 27 changes, thereby the memory cell address code appears at the output of the setting block 27 These blocks 23-26 of settings in which the switching time parameters of the next channel are stored. The clock pulses generated by the described method from the direct output of the flip-flop 21 arrive at the gate inputs of the decoders 10-12, ensuring the closure of the channels for the time of the polling rate and the opening of the previous channel before the closure of the next one for the pause time. This avoids the simultaneous closure of two channels when the previous one has not yet opened, and the next one has already closed, which can lead to the failure of the corresponding sensors at the inputs of the switched channels.

Thus, the channels are switched with an individual polling rate, which allows maximum use of the speed of each channel, automatic switching of the polling rate and pause for each channel, and allows you to simultaneously use different types

switchboards, for example, contact and contactless at the same time.

In cases where it is necessary to poll all channels with the same speed or all channels of contact cards with one speed, and all channels of contactless cards with another, a mode with a "fixed speed" is provided.

In switchboards 2.1-2.M, a special signal is set — a sign of the type of switchboard, for example, for switchboard contact cards, this may be a logical signal “O, and for contactless switchboard cards — a signal logical“ 1. This signal from the switchboard output goes to the corresponding inputs M of controlled drivers 13.1-13.M in each of the P blocks 1.1-1. P switching.

the control inputs of which are connected to the corresponding outputs of the decoder 11, which allows the signal "Switchboard sign to pass to the combined output M of controlled drivers 13.1 - 13.M in all P blocks 1.1 - 1.P switching only at the moment of polling this switchboard. If the combined inputs of the AND 34 and 35 signal have a "Fixed speed coming from a strip 39, depending on the signal" The type of switchboard type passes the signal from the input or output of the inverter 33 to the control inputs of the first or second registers 28 and 29, which, at the output of the corresponding register, forms the address of the memory cell of the setting blocks 23-26, where the parameters of the order and magnitude of the interrogation speed, the order and pause size for the contact or contactless switching board, respectively, are stored. The addresses of these memory cells are sent to the address inputs of registers 28 and 29 from address 41 before starting work, or they can be set constant, for example register 28 can store the address of the zero cell of setting blocks 23-26, and register 29 the address of the first cell.

The source of the occurrence of the control signals for the channel and the generation of the signals for the end of the operation or the sync pulse are the clock pulses from the first trigger 21.

Depending on the signal "Type of switchboard type at the control inputs of the additional controlled drivers 30 and 31, the counting input of the second counter 15 appears pulses from the corresponding output of the dividers 5. The code from the output of the second counter 15 goes to the first inputs of the comparison unit 17 On the second inputs of which there is a code for the value of the delay of the clock pulses relative to the clock pulses from the memory cell of the setpoint block 32, the address of which is specified by the code from the output of the counters 7-9, i.e. for each channel by the corresponding The address is recorded with the code of the value of the sync pulse delay in a block of 32 settings. The counting input of the second flip-flop 22 receives clock pulses from the output of the first flip-flop 21, the leading edge of which sets the second flip-flop 22 to a state that prohibits starting the measurement on the switched channel before the end of the transients in it. When the codes coincide, a pulse from the output of the second comparison unit 17 through the OR element 20 sets the second counter 1.5 to the zero state and, via the installation input, translates the second trigger 22 to the state allowing the measurement to start on the switched channel after a time determined by the delay time read from block 32 settings, individual for each channel, i.e., the signals of the sync pulse are generated with a delay relative to the clock pulses taking into account the speed of each channel and pass to the bus 38 and through the element OR 47 - to the 51. Thus, in the case of continuous polling, the signal "End of Bus 51 operation (or" Sync on Bus 38) is generated with a delay relative to the leading edge of the clock pulses and automatic change of this delay is provided, which makes it possible to use in one switch switch boards with different types of keys. The switch in the mode with multiple polling works as follows. The start signal through the OR element 18 sets the first trigger 21 to a state in which a pulse appears at its forward output, the leading edge of which is the leading edge of the first clock pulse arriving at the counting input of the counter 7, thereby setting the counters 7 -9 to the state corresponding to the address of the first channel in the loop. From the output of counters 7-9, the code of the number of the first channel goes to the inputs of the decoders 10-12, from the output of which the control signals go to the inputs of the corresponding P blocks 1.1-1.P switching, M switchboards 2.1-2.M and N channels, and the first channel is closed. The impulse from the direct output of the first trigger 21 permits reading the contents of the memory cells in the setting blocks 23 and 25, which determines the order and rate of the first channel polling rate at the address determined by the output of the setting block 27. Further, the formation of the first clock pulse, the duration of which consists of the magnitude of the polling rate and the pause size at the stage of generating the magnitude of the polling rate, is carried out similarly to that described. At the same time, the leading edge of the first clock pulse from the first flip-flop 21 sets the second flip-flop 22 to the state that prohibits starting the measurement on the switched channel before the end of the transient processes in it. After a time determined by the delay time read from the setpoint block 32, the second trigger 22 is set in the described manner to the state allowing the measurement to begin on the switched channel. This signal, via the OR 47 element, appears on bus 51 as the first-time signal on the switched channel. At the same time, the signal from the output of the second flip-flop 22 is fed to the setup input of the third flip-flop 46, the signal from the output of which through the block 50 prohibiting the absence of a signal at its second input “Continuous polling goes to the setting input of the first flip-flop 21, blocking its operation. Thus, when the code from the first counter 14 coincides with the code of the polling rate from the output of the set block 25, the pulse from the output of the first comparison block 16 through the OR 18 element does not turn the first trigger 21 into a state in which the signal from the inverse output allows it to read , the contents of memory cells in blocks 24 and 26 of the settings, which determines the order and value) i at the address determined by the output of the block 27 of the settings. As before, the signal from the direct output of the first trigger 21 allows reading the contents from the same memory cells of the setting blocks 23 and 25 and simultaneously enables the operation of the third b, y 42 comparison. At the moment of coincidence of the code of the first counter 14 and the code of the polling rate of the first channel from the outputs b, yu 25 setpoints of the polling rate at the output of the third block 42, the impulse arriving at the driver 49, which forms an impulse along its leading edge, is c, which through the element OR 47 enters the bus 51 in the form of a second imp, “End of operation, allowing the second measurement on a closed channel. Since the first trigger 21 is in its previous state, the output of the third comparison unit 42 at the time of coincidence of the code of the first counter 14 and the code of the sample polling rate appears the first.1 pulses arriving at iiniiiy 51 and determining subsequent measurements on same channel. At the same time, this sequence of pulses from the output tert:, its comparison unit 42 is fed to the counting input of the third counter 45, the code from the output of which goes to the second inputs of the fourth comparison unit 43. At the first inputs of block 43 there is a code of the number of measurements on the selected channel from the output of the block of 44 settings, read from the cell to us at the address specified by the counter code 7--9. An impulse from the output of the fourth block 43 of the comparison, determining the instant of coincidence of these codes and meaning that a specified number of measurements have been made on the short canal, sends the thirds of the checker 45 to the zero state through the OR 48 and sets the third trigger 46 to the state at KOTOJMIM, the impulse from the prohibition block 50 removes the batch from the first trigger 21, turning it into a state, and the signal from the inverse output allows reading the contents of the memory cells in the setting blocks 24 and 26, prohibits reading from the settings blocks 23 and 25 and behind stops the work of the third block 42 comparison. After forming the pause of the pern1, the three ger 21 is set to a state in which the signal from its direct output allows the reading of the contents of the memory cells in the setting blocks 23 and 25 and the operation of the third | -o comparison block 42. At the same time, the persistent front of this signal is the leading edge of the second clock pulse arriving at the input of the counter 7 and the second trigger 22, ensuring the closure of the second channel and the formation of the signal of the first and subsequent measurements on the second channel, similarly to that described.

Thus, the switch extends the functionality by setting the polling speed, pause and delay time of the clock pulses relative to the clock pulses for each channel individually, taking into account its speed, the ability to automatically switch the poll speed, the pause and delay time of the clock pulses, which makes it possible to simultaneously use the switch switch boards with different types of keys.

With the possibility of an arbitrary number of measurements on a closed channel, taking into account the first and subsequent measurements, which allows for multiple measurements on a channel with a maximum polling rate.

Claims (1)

Invention Formula Switch on AB. cb No. 1182658, characterized in that, in order to expand the functionality, two comparison blocks, a setting block, a measurement number, a counter, a trigger, two OR elements, a driver, a inhibitor block, the first inputs of the first comparison block and the output of the first the counter is connected to the first inputs of the third comparison unit, the second inputs of which are connected to the second inputs of the first comparison unit and with the combined outputs of the pause size setting block and the polling rate setting value block, the read input of the latter is connected to the read input block of the order of the polling speed, the counting input counter / V channels, gate inputs of decoders / V channels, M channel groups, P switching units, counting input of the second trigger, direct output of the first trigger and control input of the third comparison unit, the output of which is connected to the input of the imaging unit and with the counting input of the third counter , the output of which is connected to the second inputs of the fourth comparison unit, the first inputs of the latter are connected to the output of the setpoint of the number measurements, the address inputs of which are connected to the address inputs of the block of settings for the delay time of the clock pulses, the block of settings for the address of the parameters of the switching time and the outputs of counters / V channels, M channel groups, P switching units, and data inputs - with data length, the output of the fourth comparison block is connected to the first input of the fifth OR element and the second installation input of the third trigger, the first installation input of which is connected to the output of the second trigger, the sync pulse and the first input element of the fourth OR element, the second input of which is connected to the output of the imaging device, and the output - with the “End of operation, output of the third trigger is connected to the first input the prohibition unit, the second input of which is connected with the “Continuous polling” and the output with the second installation input of the first trigger, the second input of the fifth element OR is connected to the bus “Reset, and the output with the installation input of the third counter.