SU1442976A1 - Programmable controller - Google Patents

Description

(21) 4236261 / 24-24

(22) 04/27/87

8. Bul, № 45

Plant Thermoplastic Hm-nsh; whom production association Pressmash

(72) B, A, Fedorchuk; . Fitkal, B, B, Kzpssov and B, .L. Pavlov

(53) 621,503,55 (088.8)

(56) Authors: USSR certificate № 1231488, class, G 05 В 19/18, 1985

USSR author's certificate number 1208536, cl. G 05 B 19/18, J98 / 4.

(54) SOFTWARE CONTROLLER PROGRAM,

(57) The invention relates to automatic discrete control systems, in particular, can be used to control casting

processing machines for thermoplastic materials. The purpose of the invention is to simplify the programmable controller, increase reliability, and expand its functionality. A programmable controller comprising a clock generator, a counter, a block of permanent memory, a block of operational memory, a decoder of the operation code, an input block, an output block, further comprises

the second announcement, five elements AND-IE; one element 1SH11, channel switch ,, comparison unit, register, trigger. The work program is divided into. control words (CI), consisting of conditional and executive parts, and are executed only after conditional part conditions are met. Each MS starts with a microinstructed Start of Control Word (NUS). The trigger is switched to the active state each time it is read from the block of the memory of the microinstructions of the NUS and to the passive state when one of them fails. terms of conditional part of DC. If at the time of reading from the block of permanent memory of microinstructions of the executive part, the trigger remains in the active state, the microinstructions are executed, otherwise they are only read. CMUs can be linked into subroutines or individual programs using intermediate variables stored in a RAM block. This information processing principle makes it possible to simplify the programmable controller. 5 il.

(ABOUT

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Invention m-1. relates to automatic discrete control systems and can be used to control the industrial equipment of HpiBM to mechanisms, in particular, injection molds and cranes.

The aim of the invention is to simplify the controller, increase the reliability of operation and expand its functional possibilities by simultaneously controlling an arbitrary number of objects.

Fig, 1 shows the functional diagram of the programmable controller; FIG. 2 is a functional diagram of the input unit of FIG. 3 — functional diagram of the output unit of FIG. 4 - time diagrams of the programmable controller; in fig. 5 - a fragment of the program of work of the programmable controller.

The programmable controller contains a pulse generator 1, a counter 2, a permanent memory unit (ROM) 3, the first decoder 4, the element OR 5, the elements AND - NOT 6 and 1, j the second decoder Q ,, the element AND-NOT 9, the trigger ten; the element P. input 12 and output 13 blocks, the switch 14 channels, the RAM block 15 (RAM) e register 16, the comparison block 17, the H – NE 18 element, the galvanic isolation circuit 19; multiplexer 20, element HCKJlOHAIOHifEE OR 21. element 22, control input 23 of the input block, control input 24 of the input block, address inputs 25 of the input block, inputs 26 of the input of the programmable tson-roller signals, control code (line) 27 of the input block , decoder 28 of the output block, P triggers 29 of the output block, element 30 galvanically-de-energizing the output block, output keys 3i of the output block, control input 32 of the output block, address input 33 of the output block., control input 34 of the output block , ip 35 output signals controller and control outputs 36 and 37 of the output unit,

Programmable control, per works in the next way.

Generator 1 generates a sequence of clock pulses. Clock 1 adapters on the first and second outputs of the generator are shifted relative to each other 180,

0

0

-:

.

Moreover, imp LL.: S on the second output of the he-f-shratorz are shortened (fig. 4),

Counter 2 is a controller address counter and is a binary counter whose bit outputs are addressable inputs of block 3, the counter size determines the volume of block 3,

As the clock clocks get into counting 2 from oscillator 1, the address code of block 3 changes, from which the program commands sequentially from the nth program are changed. Commands consist of three parts; operating, address, and informational,

Informat.tyonna part of the team., In turn, consists of two parts: -per, g; enters the entrance block 12 and the IS block; and so; ke pa first port 14 channels, the second part of the gateway to the second input of the switchboard); 1h channels, Operational part tsomapdy postz pastes on dehgifrator 4, x torquay,: 1TG; 1eae1 signals i 1 - Khode, Bv / BOL pns / orma-, g-1K lb; csd: oi ypo K. D to the fourth: 3, / move.

The address part of the code is enrolled, za la first: input RAM 3, for the first address of the memory cell, and the first input; outgoing unit 13, a certain sweep — output, controller output . A dash input input 2, select ;; a specific controller input, as well as the input of the second depot 8, the work program which is stored in a constant-unit block I- consists of control words. A control word — its word is a set of worlds: pO instructions. In the simplest case, the control word consists of conditional and executive parts. The conditional part of the control word is described by microinstructions for entering the infor mack -; c, block I 2 and reading G pgformations from block KV. 15, Execute X, the part of the equivalent word is described by the microinstructions of outputting information to the output unit 13 and writing the information into the RAM 15, Jennolte, the flax part T of the equal of the word is executed only if the conditional control part is executed ya with

The control code word starts with a microinstruction: Start of the control word (CCP) (Fig. 5). The N-e control word consists of several conditional and executive parts. The first conditional part includes microinstructions Input 1 and Read 1. The second conditional part includes Read, 2, Read 3 and Input 2, B, the first executive part includes Microinstructions Впзод 1. The BTOpoii executive part, Conclusion 2, Record D and Record 2. Perv is-. The complementary part of the control word is performed only after the steam condition of the part of this word is fulfilled, 1g ish; it is used; the telpl part of the control word is only after the first and second conditional parts of the tear control have been completed. (N + l) - e control 1G) The 1st word is only from three Hror. Instructions.,

Suppose that in ra. -G; The scan address of the block 3 of the permanent memory at the time t on the internal bus of the controller is transmitted to the code of the microtool NUS, stored at address Ai. Then, a logical unit signal is generated at the output of the decoder -8 and the clock iguls from the generator I through the IS-NE element 9 are fed to the S input of the trigger 10, the Trigger 10 is set to the active state, and from its output the signal of the logical unit arriving at the third input of the element AND-NOT 6 and the third input of the element AND-NOT 7 ,,

At time tj, microinstructions Input, 1 is sent to the internal bus of the controller. Suppose that this microinstruction describes the operation of directly testing the input of unit 12. The result of polling the i-input comes through the control line 27 to the third input of the AND-NOT element 11. If the input signal is present at the LM input at the time of the microinstruction input (i.e., the state of the input being tested matches the state of the input instruction), line 27 sets the logic zero signal and the state of the trigger 10 does not change. Element EXCLUSIVE WDI 2G input unit 12 is designed to implement two types of input signal testing (direct testing

976

entering or testing his dog1). The type of testing is determined by the signal received at the control input 24 of the input unit 12,

At the moment of time, the micro-instrument of Reading 1 is output to the internal bus of the controller. Execution

microinstructions reading occurs

.in the following way. The contents of the memory cell 15 with the address indicated in the address part of the microinstruction is placed in register 16. At the same time, the contents of the same

The cells are fed to the first input of the comparator block 17. At the second input of the comparator block 17, the contents of the structural part are fed out: if the two operands are equal, then at the input of the AND-NOT element

a logical zero signal is set to the TpeTiifr input

element AND NOT 11, which prohibits switching; tremgger Yu, at the R input.

TaKiLM way, trigger-10. According to S-BXO, it can be set to the actuation state when outputting to the internal bus — o: a trolley for the microsystem, and to the passive state. - by

R-input when the condition described by the micro-tools of the conditional part is not fulfilled. In the example, both micro-instructions of the conditional part of the control word are executed, and therefore the 1 O flip-flop remains active, allowing further execution of the executive part. Therefore B moment of time

MICRORSTRUCTURE Pin 1 EXT Yatts, D-flip-flop 29 of output block 13, select the address part of the IP-instructions Vyogod 1, is set to the state, which is determined by the control of the gig signal received in output block 13 by input 32. This signal refers to informational part of microinstruction. Execution of microinstructions Reading 2, Reading 3 and Entering 2 into the following

times are similar. Assume that microinstr. Input 2 is not executed, then in this step the trigger 10 is set to the passive state, and at the third inputs of the AND-NE elements 6 and 7 a logic zero signal appears, and the execution of the microinstruction Output when reading the current control word is prohibited, although when scanned ;; ,

51

addresses of block 3 they and vysho ts on the internal bus controller.

When the microinstruction of the NUS is output to the internal busbar bus, the first decoder 4 is blocked by a signal from the output of the decoder 8 and no signals are generated at the control outputs of the decoder 4.

The RAM block I5 is designed to store intermediate results of solving logical equations H1-sh, with which the individual control words are linked in

mti, the outputs of the address code which is connected to the address inputs of the input unit, output unit and block

RAM, as well as a first decoder, a comparison unit, an OR element, and a CK trigger, characterized in that. In order to simplify the controller, increase the reliability of the operation and enhance the functionality due to the simultaneous independent control of an arbitrary number of objects, a commutator of channels has been entered into it, the second

subroutines and separate independent 15 encoder, five AND-NOT elements and reprograms.

In block 5, the settings of the technological parameters of the operating cycle of the controller and of the current information are stored in software-implemented counters and timers.

For this purpose, the possibility of changing the register 16 by +1 using the control outputs 36 and 37 of the output unit 13 is used.

Depending on the operation modes of the switch 14, the information for recording e block 15 may be the contents of the registers 16 or the contents .. in.

The number and length of control words 5 located in ROM 3 depends on the amount of memory and on the complexity of the algorithms of control objects and, in general, can be arbitrary.

The principle of processing information and organizing teams about

 allow to significantly reduce hardware costs and the required memory capacity of the permanent storage device, provide multi-program operation without additional hardware costs, accept execution. The program can occur in any sequence specified by the operator at the same time, which ensures control of several independently operating mechanisms, equipment.

Claims (1)

Invention Formula A programmable controller containing a clock pulse generator, a pulse counter, the information outputs of which are connected to the address inputs of a constant-voltage block. the gist, whose vodosd is connected to the first input of the channel switch, the first and second inputs of the register are connected respectively to the first and second outputs of the output block, and the third input to the nepBFjiM input of the first element, to the first input of the IPI element and to the first output of the first decoder, The second output of which is connected to the second input of the OR element and to the second input of the input unit, the TpeTi-rfi output of the first decoder is connected to the first input of the second AND element — the fourth output from the first Bbtt-5 input of the third NAND element. whose second input is connected to the second) 1m input of the second NAND element, with the first inputs of the fourth and fifth NAND elements and with the first output clock generator, the second output of which is connected to the information input of the Sh-pulse counter, the third input of the second IS-NOT element is connected to the third input of the third IS-NOT element and to the RS-flip-flop output, the S-input of which is connected to the fourth output element NAND, R- input - with the output of the nth element NAND, the second input of which is connected to the output of the IDN element, the third input to the first NAND element and to the output of the input block, the output of the third AND-NOT element is connected to the third input of the output block, the output of the second AND-NOT element is connected to the BTOpbiM input of the block RAM, third input - with the output of the channel switch and with the first input of the comparison unit, the second input of which is connected to the output of the RAM and the fourth input of the register, the code of the comparison unit is connected to the second input of the first NAND, second entrance icoMi-iyTa go one  one t; j.OT -.-- „I.I, Ii j 33 Ij- - “™  g L .L,., & l s "P-i / a J f Ii IL.r.,:: ,, - .. r L V - J, L , t- C, drove on the first pin of generator 1 Signal to counter / (a Z about with ig and a / 1 on the Second You), 1 generator of 1 tii2Hafi on desh, and (ppra pore8 C (4ZHu / i on Oh / course 1 deshi, (Rrap7ora / C (n "/ Sbf) (2 descriptors Сц, гнаи на Вь1) ode Ves Shchratora Signal on you code 3 dec and p & torus " Signal / on Bifixode t rig 2 ep a 10 Signal / j at the output of the element AND NOT 1 The signal at the output of the element AND-HE5 9vi. L / f / Ifftf ., about  S L / tt-f L / fTf JINY & / f i / r Aia