SU1264134A1

SU1264134A1 - Common time system

Info

Publication number: SU1264134A1
Application number: SU833546080A
Authority: SU
Inventors: Фагильсон Галеевич Мухаметов
Original assignee: Mukhametov Fagilson G
Priority date: 1983-01-31
Filing date: 1983-01-31
Publication date: 1986-10-15

Abstract

Изобретение относитс к приборостроению и позвол ет повысить надежность управлени вторичными часами. Опорный генератор 3, синхронизируемый от сети переменного тока, формирует импульсы, которые поступают на входы элементов И-НЕ 6 и 9 и элемента И 15. При достижении очередной минуты импульсом с выхода первичных часов 2 триггер 17 устанавливаетс в единичное состо ние, после чего с выхода элемента И-НЕ 6 импульсы опорной частоты через элемент И-НЕ 7 поступают на вход вторичных часов 8. На выход элемента И-НЕ 7 проход т первые три импульса. С выхода элемента И-НЕ 4 сигнал после инверсии поступает на один из входов элемента И-НЕ 6, а с выхода элемента И 15 импульсы поступают на вход счетчика 11, результат считывани импульсов текущего времени сравниваетс элементом 19 сравнени кодов с кодом текущего времени, поступающего с выхода счетчика минут и часов первичных часов 2. В результате сравнени формируетс сигнал логической единицы, запирающий элемент И 15, прекраща поступление импульсов опорной частоты на вход счетi чика 11. Приведено описание работы вторичных часов 8. 2 ил. (Л Nd О) 4 СО 1The invention relates to instrumentation engineering and makes it possible to increase the reliability of controlling the secondary clocks. The reference oscillator 3, synchronized from the AC network, generates pulses that are fed to the inputs of the elements AND-NOT 6 and 9 and the element 15. When the next minute is reached, the pulse from the output of the primary clock 2 causes the trigger 17 to be in one state, after which the output of the element AND-NOT 6 pulses of the reference frequency through the element AND-NOT 7 arrive at the input of the secondary clock 8. The output of the element AND-NE 7 passes the first three pulses. From the output of the element AND-NOT 4, the signal after inversion arrives at one of the inputs of the element AND-NOT 6, and from the output of the element 15, the pulses arrive at the input of the counter 11, the result of reading the pulses of the current time is compared by the element 19 of the code comparison with the code of the current time from the output of the minutes counter and hours of the primary clock 2. As a result of the comparison, a logical unit signal is formed that locks the AND 15 element, stopping the arrival of the reference frequency pulses at the input of the counter 11. A description is given of the operation of the secondary clock 8. 2 Il. (L Nd O) 4 CO 1

Description

Изобретение относитс к приборостроению , а именно к системам единого времени.This invention relates to instrumentation engineering, in particular to single time systems.

Цель изобретени - повышение надежности ynpasjeKHH вторичными часами.The purpose of the invention is to increase the reliability of the ynpasjeKHH secondary clocks.

На фиг. 1 и 2 приведены структурные схемы системы единого времени и вторичных часов.FIG. Figures 1 and 2 show the block diagrams of a single time system and secondary clocks.

Система единого времени содержит блок 1 управлени первичными часами, подключенный выходом к входу первичных часов 2, опорный генератор 3, первый элемент И-НЕ 4, подсоединенный выходом через первый элемент НЕ 5 к первому входу второго элемента И-НЕ 6, третий элемент И-НЕ 7, соединенный выходом с входом вторичных часов 8, четвертый элемент И-НЕ 9, первый и второй счетчики 10 и 11, второй, третий и четвертый элементы НЕ 12, 13 и 14 и первый и второй элементы И 15 и 16.The unified time system contains a primary clock control unit 1, connected by an output to an input of primary hours 2, a reference generator 3, the first AND-NO 4 element, connected by an output through the first NO 5 element to the first input of the second IS-NOT 6 element, the third AND- element NOT 7, connected to the output of the secondary clock 8, the fourth element AND-NOT 9, the first and second counters 10 and 11, the second, third and fourth elements NOT 12, 13 and 14 and the first and second elements 15 and 16.

Система единого времени также содержит первый и второй триггера 17 и 18, элемент 19 сравнени кодов, элемент 20 задержки и формирователь 21 импульсов, причем первый триггер 17 подключен первым входом через формирователь 21 импульсов к первому выходу первичных часов 2, вторым входом к соединенным между собой входам второго счетчика 11, установочному входу первого счетчика 10 и инверсному выходу второго триггера 18, подсоединенного выходом через элемент 20 задержки к его же установочному входу и счетным входом через второй элемент НЕ 12 - к выходу четвертого элемента И-НЕ 9, подключенного выходом к первому входу третьего элемента И-НЕ 7, первым входом через третий элемент НЕ 13 - к соединенным между собой выходу второго элемента И 16 и первому входу первого элемента И 15, вторым входом - к соединенным между собой выходу первого элемента И-НЕ 4 и второму входу первого элемента И 15 и третьим входом - к соединенным между собой первому выходу опорного генератора 3, второму входу второго элемента И-НЕ 6 и третьему входу первого элемента И 15, подсоединенного выходом к установочному входу второго счетчика И, подключенного выходами к первым входам элемента 19 сравнени кодов, соединенного вторыми входами со вторым выходом первичных часов 2 и выходами со входами второго элемента И 16, при этом первый триггер 17 подключен выходом к третьему входу второго элемента И-НЕ 6, выход которого через четвертый элемент НЕ 14 соединен с входом первого счетчика 10 и непосредственно соединен с вторым входом третьего элемента И-НЕ 7, а первый элемент И-НЕ 4 подключен входами к выходам первого счетчика 10.The common time system also contains the first and second triggers 17 and 18, the code comparison element 19, the delay element 20 and the pulse shaper 21, the first trigger 17 being connected by the first input through the pulse shaper 21 to the first output of the primary clock 2, the second input to the interconnected the inputs of the second counter 11, the installation input of the first counter 10 and the inverse output of the second trigger 18 connected by the output through the delay element 20 to its installation input and the counting input through the second element NOT 12 to the output of the third element AND-HE 9, connected by the output to the first input of the third element AND-NOT 7, the first input through the third element NOT 13 to the interconnected output of the second element AND 16 and the first input of the first element 15, the second input to the connected between the output of the first element AND-NOT 4 and the second input of the first element 15 and the third input to the interconnected first output of the reference generator 3, the second input of the second element AND-NOT 6 and the third input of the first element 15 connected to the installation input second sche And connected to the first inputs of the code comparison element 19, connected by the second inputs to the second output of the primary clock 2 and outputs to the inputs of the second element AND 16, the first trigger 17 being connected to the third input of the second element IS-HE 6, the output of which through the fourth element HE 14 is connected to the input of the first counter 10 and directly connected to the second input of the third element NAND 7, and the first element NAND 4 is connected by inputs to the outputs of the first counter 10.

Вторичные часы 8 содержат счетчик 22 секунд , счетчик 23 минут и часов, элементы 24 пам ти, делитель 25 частоты, опорный генератор 26, счетчик 27 импульсов, формирователь 28 импульсов, D-триггер 29, первый , второй и третий элементы И 30, 31 и 32 и элемент И-НЕ 33 и индикатор 34, причем опорный генератор 26 соединен выходом с первыми входами первого элемента И 30 иSecondary hours 8 contain a counter of 22 seconds, a counter of 23 minutes and a clock, memory elements 24, frequency divider 25, reference generator 26, pulse counter 27, pulse shaper 28, D-flip-flop 29, first, second and third elements And 30, 31 and 32 and the element AND-33 and the indicator 34, and the reference generator 26 is connected to the output of the first inputs of the first element And 30 and

элемента И-НЕ и с входом делител 25 частоты, выход которого соединен с счетным входом счетчика 22 секунд, второй и третий элементы И 31 и 32 подключены первыми входами к входу вторичных часов 8 и вторыми входами подсоединены к инверсному и пр мому выходам D-триггера 29 соответственно , подключенного счетным входом к выходу второго элемента И 31, пр мым выходом - к входу формировател 28 импульсов и установочным входом - к пер , вому выходу и к установочному входу счетчика 27 импульсов, соединенного входом с выходом третьего элемента И 32, вторым выходом - с вторым входом первого элемента И 30 и с вторым входом элемента И-НЕ 33 и третьим выходом - с третьимelement AND-NOT and with the input of the frequency divider 25, the output of which is connected to the counting input of the counter for 22 seconds, the second and third elements 31 and 32 are connected by the first inputs to the input of the secondary clock 8 and the second inputs are connected to the inverse and forward outputs of the D-flip-flop 29, respectively, connected by a counting input to the output of the second element I 31, direct output to the input of the pulse shaper 28 and a setting input to the first output and to the installation input of the pulse counter 27 connected by the input to the output of the third element 32 and the second output ohm - to a second input of the first AND gate 30 and to a second input of AND-NO element 33 and to third output - with a third

0 входом первого элемента И 30, подключенного выходом к счетному входу счетчика 23 минут и часов, подключенного установочными входами к выходу элемента И-НЕ 33, при этом формирователь 28 импульсов подсоединен выходом к установочным входам0 the input of the first element And 30, connected by the output to the counting input of the counter 23 minutes and hours, connected by the installation inputs to the output of the element AND-NOT 33, while the driver 28 pulses connected by the output to the installation inputs

5 счетчика 22 секунд и к синхронизирующим входам элементов 24 пам ти, соединенных информационными входами с выходами счетчика 23 минут и часов и выходами с одними входами индикатора 34, другие входы которого подключены к выходам счетчика 22 секунд.5 counter 22 seconds and to the synchronization inputs of the memory elements 24, connected by information inputs with the counter outputs 23 minutes and hours and outputs with one of the indicator inputs 34, the other inputs of which are connected to the counter outputs for 22 seconds.

Система единого времени работает следующим образом.The system of a single time works as follows.

, Опорный генератор 3, синхронизируемый от сети переменного тока, формирует импульсы с частотой следовани 100 Гц, которые поступают на входы второго и четвертого элементов И-НЕ 6 и 9 и первого элемента И 15, которые по другим входамThe reference generator 3, synchronized from the AC network, generates pulses with a following frequency of 100 Hz, which are fed to the inputs of the second and fourth elements AND-NOT 6 and 9 and the first element AND 15, which are through the other inputs

блокированы сигналом логического нул . При достижении очередной минуты импульсом с выхода первичных часов 2 первый триггер 17 устанавливаетс в единичное состо ние, после чего с выхода второго элемента И-НЕ 6 импульсы опорной часто ты через третий элемент И-НЕ 7 поступают на вход вторичных часов 8. Одновременно с этим импульсы опорной частоты подсчитываютс первым счетчиком 10 и после окончани третьего импульса на выходе первогоblocked by a logical zero signal. When the next minute is reached, the pulse from the output of the primary clock 2 is set to the first trigger 17, after which the output pulses of the reference frequency from the output of the second element AND-NOT 6 through the third element AND-NOT 7 arrive at the input of the secondary clock 8. At the same time the reference frequency pulses are counted by the first counter 10 and after the termination of the third pulse at the output of the first

Q элемента И-НЕ 7 формируетс сигнал логического нул , которым запираетс второй элемент И-НЕ 6. Таким образом, на выход третьего элемента И-НЕ 7 проход т первые три импульса. С выхода первого элемента И-НЕ 4 сигнал после инверсииThe Q element of the NAND 7 generates a signal of the logical zero, which locks the second element of the NAND 6. Thus, the first three pulses pass through the output of the third element NAND 7. From the output of the first element AND-NOT 4 signal after inversion

Claims

5 arrives at one of the inputs of the second element AND-NOT 6, and from the output of the first element AND 15 pulses arrive at the input of the second counter 11. After the second counter calculates 11 pulses of the current time, the counting result is compared by the code comparison element 19 with the current time code the minutes and hours of the primary clock 2 coming from the outputs. As a result of a comparison, at the output of the code comparison element 19 of the codes a signal of a logical unit is formed, forming at the output of the second element AND 16 a signal of a logical zero, which locks the first element 15, stopping the arrival of the reference frequency pulses at the input of the second counter 11. The output of the second element 16 jla output of the fourth element AND-HE 9 generates a corresponding reference frequency pulse, which through the third element AND-NOT 7 enters the input of the secondary clock 8, and also sets the second trigger 18 to the one state, with the result that the first trigger 17 and the counters 10 and 11 are set to the zero state. After the time delay set by the element 20, the second trigger 18 is set to the zero state, as a result of which all the elements are reset. The reference generator 26 of the secondary clock 8, synchronized from the AC network, generates pulses with a following frequency of 100 Hz, which with the help of the frequency divider 25 is reduced to a frequency of 1 Hz. When the next minute is reached, four pulses arrive at the inputs of the second and third elements I 31 and 32 at the output of the primary clock system 2, and the D-flip-flop 29 is set to one state from the front of the first pulse, and the second element 31 is locked by the signal from its inverse output , prohibiting the passage of the following pulses to the input of the D-flip-flop 29. Simultaneously with the installation of the D-flip-flop 29, a short pulse is generated at the output of the pulse shaper 28, with which the 22-second counter is set to the zero state, and in the memory elements 24 These will rewrite the states of the counter for 23 minutes and hours. The pulses from the inputs of the secondary clock 8 through the third element AND 32 are counted by the pulse counter 27, as a result of which the second pulse counts at the output of the AND-NE element 33, which sets the counter 23 minutes and hours to the zero state. After the appearance of the third pulse at the input of the counter 27 of the pulses at the output of the first element and 30, signals of the logical unit are formed, which allow the passage of the pulses of the reference frequency to the input of the counter for 23 minutes and hours. After counting a predetermined number of reference frequency pulses corresponding to a specific value of the current time, and the appearance of the fourth pulse at the input of the secondary clock 8, the D-flip-flop 29 and the pulse counter 27 are set to zero, and the counter 23 minutes and hours remain filled until the next minutes for rewriting to memory elements 24. Indicator 34 displays the current time from the 22 second counter outputs and the memory elements 24. The use of the invention makes it possible to significantly increase the reliability of control of the secondary clocks as compared with the base object. Claim 1. A single time system comprising a primary clock control unit, connected by an output to an input of a primary clock, a reference generator, a first NAND element, connected by an output through a first element NO to a first input of a second element NAND, a third element NAND connected by the output to the input of the secondary clock, the fourth element IS-NOT, the first and second counters, the second, third and fourth elements NOT and the first and second elements AND, characterized in that, in order to increase the reliability of control of the secondary clocks, The first and second triggers, the code comparison element, the delay element and the pulse shaper, the first trigger are connected by the first input through the pulse shaper to the first input of the primary clock, the second input to the interconnected inputs of the second counter, the setting input of the first counter and the inverse output of the second trigger connected by an output through a delay element to its own installation input and a counting input through a second element NOT to the output of the fourth NAND element connected by the output to the first input The third element is NAND, the first input through the third element is NOT to the interconnected output of the second element AND to the first input of the first element AND, the second input to the interconnected output of the first AND element and the second input of the first AND element and the third input to interconnected to the first output of the reference generator, the second input of the second NAND element and the third input of the first element AND connected by the output to the installation input of the second counter connected by the outputs to the first inputs of the code comparison element, unity vtorym- second inputs to the output of the primary clock, and outputs to the inputs of the second AND gate, said first flip-flop output is connected to the third input of the second AND-NO element whose output via the fourth element is coupled to the input of the first counter is connected directly and

with the second input of the third element NAND, and the first element NAND is connected by inputs to the outputs of the first counter.

2. The system of a single time according to claim 1, characterized in that the secondary clock contains a seconds counter, a minutes and hours counter, memory elements, a frequency divider, a reference oscillator, a pulse counter, a pulse shaper, a D-flip-flop, first, second and the third AND elements and the NAND element and the indicator, the reference oscillator being connected to the first inputs of the first AND element and the NAND element and to the input of the frequency divider, the output of which is connected to the counting input of the seconds counter, the second and third AND elements are connected the first inputs to the input of the secondary clock and the second inputs are connected to the inverse and direct outputs of the D-flip-flop, respectively, connected by a counting input

To the output of the second element I, the direct output to the input of the pulse former and the installation input to the first output and to the installation input of a pulse counter connected by the input to the output of the third element I, the second output to the second input of the first element I and to the second input of the element AND-NOT and the third output - with the third input of the first element AND, connected by an output to the counting input of the counter of minutes and hours, connected by installation inputs to the output of the element AND-NOT, while the pulse shaper is connected by an output to the installation inputs of the seconds counter and to the synchronization inputs of the memory elements connected by information inputs with the minutes counter outputs and hours and the outputs with one indicator inputs, the other inputs of which are connected to the seconds counter outputs.

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