SU1257838A1 - Synchronous counter - Google Patents

Abstract

The invention relates to digital computing and discrete automation. It can be used in the construction of counting devices on potential logical elements. The purpose of the invention is to increase the reliability of the operation. In the device containing 1-1 and 1-2 clock tires, bits 2-1, 2 (p-1), 2p, 2 (n + 1), each of which contains a sync input and transfer output, and each bit d, except for 2-1, contains a carry input, n-th bit contains RS (RS) flip-flops 3.4.5, to achieve the goal, an additional logical element OR NONE (AND-NOT) 9 is introduced into the n-th bit. The description of the invention shows a variant of constructing the n-th bit of a counter on the AND-NAND logic elements. The device works reliably, provided that the sum of the delay between pulses on buses 1-1 and 1-2 of the response time of element 9 is less than the pulse duration. The device provides reliable operation with any bits, the signals at the outputs of which carry over switches on a slice (front) of pulses on the clock tires. 3 il. (O (L 2-1 2-2 / - / 1-2 2- / 7 2 -fn l to ate sj 00 00 00

Description

The invention relates to digital computing and discrete automation and can be used in the construction of counting devices on potential logic elements.

The purpose of the invention is to increase the reliability of the operation.

Figure 1 shows a synchronous counter, the nth digit of which contains an additional AND-NOT element; FIG. 2 shows an example of construction on the NAND elements of the nth digit of the counter; FIG. 3 is a timing diagram of the synchronous counter operation.

The counter (figure 1) contains the first 1-1 and the second 1-2 clock spins and bits 2-1, 2-2, .. 2. (n-1), 2.P, 2. (n-b1) , .--, each of which contains a sync input and a transfer output, and each bit, except the first 2.1, contains a transfer input that is connected to the transfer output of the previous bit, the first clock 1-1 is connected to the sync inputs the first n bit Dov 2.1, ..., 2. p. The second clock bus 1.2 is connected to the synchronous inputs of all, starting with (n- | -1) -th, bit 2. (nfi) .. The first bit contains the first 3, second 4 and third 5 RSJRS) triggers, the first the output of the first RS (RS) -Tpnrrega 3 is connected to the S (S) input of the second RS {RS) - three 4, the second output of which is connected to the RjR) inputs of the first 3 and third RS (RS) triggers, the first output of the third RS (RSi-Tpnr repa 5 is connected to the S (S) input of the first RS (RS) trigger 3, the second output of which is connected to the S (S) input of the third RS (RS) flip-flop 5, transfer 6 is connected to R (R) and S (S) -inputs of the first RS | RS) -trigger 3, synchronous input 7 is connected to the R (R) - input the first 3 and second 4 RS (RS) triggers, and the output of the transfer 8 connects with the first output of the second trigger 4, the n-th bit 2-n contains an additional logical element OR NOT (AND-NO) 9, the first input The second input of the additional logic element 9 is connected to the second clock bus 1.2, and the output of the element 9 is connected to the S (S) input of the first trigger 3.

Figure 2 shows an example of constructing the n-th bit of a counter (figure 1) on logical E; I-NEs, the n-th bit contains three RS-flip-flops 3-5, transfer input b, sync-input 7 and transfer output 8, and also an additional logical e; 1 IS output-NE 9. The first trigger 3 is built on the elements AND- NG: 10 and 1, the second trigger 4 - on the elements AND-NO 12 and 13, and the trigger 5 - on the e-cell 11 X AND-NO 14 and 15.

Similarly, it is possible to construct the n-th bit on the l () - ilic elements OR NOT.

The operation of the synchronous counter (Fig. 1) is explained in the time diagram of Fig. 3. In the initial state at the outputs of the first 2.1 and {n-fl) -r () 2. (n -) - 1) bits vcranoBjieiibi signals. yugic Oh, and on

0

five

outputs of transfer of all bits and s.;. odds Q bits from the second 2.2 to n-th 2.n are signals of a logical unit. The signals on the clock tires 1.1 and 1.2 are depicted with a phase shift. On the front of the first pulse 1-1, the signal Q of the first bit 2.1 is switched to a logical unit. On the front of the first pulse 1-2, the element 9 is switched to the logical zero. Over a slice of the first pulse, sequential switching to a logical unit occurs. signals at the outputs of the first (n-1) bits of 2.1 ..., 2. (n-1). The dotted line in the timing diagram shows the possible switching signals on the first outputs of the first 3 and second 4 RS (RS) triggers of the nth bits, which would occur in the absence of element 9. The occurrence of a logical low on the first output of the second RS (S) is dangerous. - trigger 4 n-th bit during action

0 pulse on bus 1-2, which can lead to a false positive (n + O-th bit. However, the logical zero signal at the output of element 9 holds the logical unit at the first output of the first RS (RS) trigger 3 until the pulse is cut on the bus

5 1-2. Further switching occurs in accordance with the timing diagram (Fig. 3). In the case of the opposite distribution of delays between pulses on buses 1.1 and 1.2, dangerous situations do not occur, since the pulse front at the n-th bit transfer output cannot outrun the pulse slice by 1.2.

The synchronous counter operates functionally reliably, provided that the sum of the delay between the pulses on the buses 1.1 and 1.2 and the response time of the element 9 is shorter than the pulse duration.

Thus, the proposed synchronous counter with the n-th bit made on the AND-NOT (OR-NOT) elements ensures reliable operation with any bits, the signals at the outputs of which are switched along the edge (edge) of the pulses on the clock tires.

Claims (1)

Invention Formula 5 A synchronous counter, the contents of the first and second clock and bits, each of which contains a synchronous input and transfer output, and each bit, except the first, contains a transfer input, which is connected to the transfer output of the previous bit, the first clock bus is connected to the sync inputs of the first n bits, and the second 1 pin clock is connected to the sync inputs of all, starting with (n + 1) th bits, the nth bit contains the first, second and third RS (RS) -triggers, the first output of the first RS (RS) -trigger is connected to the S (S) -input of the second RS (RS) -trigger, the first output of which is connected to the transfer output n-th 0 five 0 0 bit, and the second output is connected to the R (R) -inputs of the first and third RS (RS) - triggers, the first output of the third RS (RS) - trigger and is connected to the S (S) -input of the first RS () trigger, the second the output is connected to the S (S) input of the third RS (RS) - three gage, the transfer input is connected to the R (K) and S (S) inputs of the first RS (RS) trigger, the sync input is connected to the R (R) -inputs of the first and second RS (RS) triggers, differing By the fact that, in order to increase the reliability of the operation, the nth bit contains an additional logical element OR NOT (NAND), the first input of which is connected to the first output of the first RS (ITS) trigger, the second input of the additional element is connected to the second clock bus, and the output of the additional element is connected to an additional 5 (5U-input of the first RS (RS) - trigger.