SU1243020A1 - Device for restoring reproduced clock pulses - Google Patents

Abstract

The invention relates to the field of accumulation of information, namely, devices for the recovery of reproduced clock pulses. The purpose of the invention is to increase the accuracy of the recovery of the reproduced clock pulses. The device contains elements AND 1 and 6, a source of 2 clock pulses, elements OR 3, 7 (L Is9 i CA9 figure 1

Description

and 8, shaper 4 of the sign of the beginning of information, counter 5, triggers 9 and 10, pulse generator 11, shaper 12 of the sign of the end of information, the decoder 13 and shapers 14 of information pulses. The device also contains triggers 16 and 18, a decoder 17, elements OR 19-22, elements AND 23 and 28, and correction blocks 24, each of which is made

The invention relates to the field of accumulation of information, namely, devices for recovering reproduced clock pulses.

The purpose of the invention is to improve the accuracy of the recovery of reproduced clock pulses.

Fig. 1 is a diagram of an apparatus for recovering reproduced clock pulses, an embodiment; figure 2 - scheme. pulse trainer, option.

The device contains the first element And 1 connected by the first input to the output of the source 2 clock pulses and connected by the output to the first input of the first element OR 3 connected by the second input to the output of the imaging unit 4 of the sign of the beginning of information, the counter 5, the second element And 6, the second 7 and the third 8 elements OR, the first 9 and second 10 triggers, the generator 11 pulses, the second shaper 12 sign of the end of the information, the decoder 13 and the shapers 14 pulses of information. The output of the first element OR 3 is connected to the input of the installation of the logical zero of the counter .5 and to the first input of the second element OR 7, which is connected by output to the installation inputs of the logical unit of the first 9 and second 10 triggers.

The first and second inputs of the second element And 6 are connected respectively to the first OUTSHINE of the pulse generator 11 and to the output of the first trigger 9, connected by an input of the form of correctors consisting of shapers of 25 series of pulses, a decoder 27, Introduction of new elements and the formation of connections between the device elements allows to increase the accuracy of the recovery of the re-generated clock pulses. The description discloses one of the possible variants of a pulse trainer. 1 з, п.ф-л, 2 Il.

novki logical zero with the output of the shaper 12 sign of the end of the information. The third element OR 8 is connected by an output to the output bus 15 clock pulses and connected by the first input to the overflow output of the counter 5, the outputs of which bits are connected to the inputs of the decoder

13. The output of the decoder is connected to

the installation of the logical zero of the second trigger 10 connected by an inverse output with the second input of the first element And 1.

The device also contains a third trigger 16 connected by the installation of the logical unit with the output of the decoder 13, an additional decoder 17, connected between the outputs.

the bits of the counter 5 and the second input of the second element OR 7, the fourth trigger € 18, connected by the installation input of the logical unit to the overflow output of the counter 5, a quarter,

five, the sixth and seventh elements OR 19-22, the third element And 23 and blocks of 24 correction, each of which is made in the form of correctors, consisting of the formers of 25 series of impulses

connected by the first input bus 26 to the second output of the generator 11 pulses, and from the connected in series decoders 27, connected: inputs to the outputs of bits

counter 5, and elements And 28.

The fourth element OR 19 is connected by the first input to the output of the second element AND 6 and is connected by an output to the sum 1: the remote input of the counter 5. The output of the fifth element OR 20 is connected to

subtractive input of the counter 5. The first input of the sixth element OR 21 is connected to the output of the first element AND 1 The output of the third element AND 23 is connected to the second, the input of the third element OR 8, the output of the seventh element OR 22 - to the second input of the sixth element OR 21 and to the second the input of the fourth element OR 19, the Sixth element | MENT OR 21 is connected by the third input to the output of the fifth element OR 20 and is connected to the input of the logical zero setting of the fourth trigger 18, the output of which is connected to the first inputs of the elements 28 of the equalizers of the 24 correction blocks ii. The output of the first element And 1 is connected to the first. the input of the third element And 23 connected by the second input to the output of the third trigger 16.

The input of the installation of the logical zero of the third trigger 16 is connected to the overflow output of the counter 5, the second inputs of the elements AND 28 offsets of each correction block 24 are connected to the output of one of the drivers 14 of information pulses. The output element And 28 of each corrector. /. Correction blocks 24 are connected to the second input bus 29 of one of the shapers of 25 pulse series. The inputs of the fifth element OR 20 are connected to the output buses 30 of the drivers of 25 series of pulses of one half of the correctors of each correction unit 24. The inputs of the seventh element OR 22 are connected to the output tires of 30 formers of 25 series of pulses of the other half of the correctors of each block 24 of correction,

Each shaper 25 of a series of pulses of the equalizer of the correction unit 24 contains the first, second and third D-flip-flops 31-33 connected by synchronization inputs to the first input bus 26, RS-flip-flop 34, connected by the installation input of logical one 1 with the second in one bus 29 , and element 35, connected by output to output bus 30, the output of the RS flip-flop 34 is connected to the information input of the first D-flip-flop 31 connected to the output of the first input of the element 35 and to the information input of the second B-flip 32 Direct output of the second D-Trig Gera 32 plots dinene to the information input of the third D-flip-flop 33, soy

5 Yu t5, 20

25 ..

5 0 5

five

the inverse of the output with the input of the installation of logical zero RS-flip-flop 34, the second input element And 35 is connected to the first input bus 26.

The device works as follows.

The signal of the sign of the beginning of information from the output of the forcer 4 of the sign of the beginning of information, having passed through the first element OR 3, sets the counter 5 to the zero state. This signal also passes through the second element OR 7 and confirms the single state of the first flip-flop 9, and also sets the second flip-flop 10 to the single state. In this case, the pulses of the pulse generator 11 pass through the second element AND 6 and the fourth element OR 19 to the counter 5, the width of the counter 5 establishes with the condition that it is filled: it occurs in a time equal to the calculated period of the clock pulses. The counter 5 provides the triggering of the decoder 13, which sets the second trigger 10 to the zero state, and the third trigger 16 to the one state. At the same time, each clock pulse from the source output 2 clock pulses, passes through the first element AND I and the first element OR 3 and sets the counter 5 to the zero state. The same clock pulse passes through the sixth element OR 21 and translates the fourth trigger 18 to the zero state. The level of logical zero from the fourth trigger 18 affects the elements And 28 of all offsets of each correction unit 24, which ensures the prohibition of the correction of the recovered clock pulses. Each clock pulse, in addition, passes through the second element OR 7 and confirms the single state of the first trigger 9, and also places the second trigger 10 into the single state by the falling edge. The second trigger 10 prohibits the arrival of clock pulses from a source of 2 clock pulses through the first element I 1 until the next operation of the decoder 13.

If the clock pulse arrived before the counter overflows 5, then it passes through the first element And 1, the third element And 23 and the third element

OR 8 per output bus 15 clock pulses. If the clock pulse is not received before the counter overflows, then the pulse from the overflow output sets the third trip 16 to the zero state, and the fourth trigger 18 to the one state and passes through the third element OR 8 to the output bus 15 clock pulses,

The third trigger 16 prohibits the clock pulse xoxgqeiiHe through the third element 23, the 4th trigger 18 acts on the elements 28 of all the correctors of the correction block 24, which allows the correction of the clock interval of signals received from the drivers of 14 information pulses. In every way the corrector of any correction unit 24, the information pulse of the corresponding shaper 14 of information shifts, when it coincides with the signal of the corresponding decoder 27, starts the corresponding shaper of the 25 series of pulses. At the same time, in each form of a 25-series pulse generator, its output pulses are synchronized by a pulse sequence received from the generator of 11 pulses.

In the variant of the generator of the 25 series of pulses (Fig. 2), the pulse from the AND 28 element sets the RS-flip-flop 34 to the unit 1Native: the 5-th pulse of the generator 1 I I1-1Gsulsov with its falling edge sets the first one to the trigger 31 in a single cocroHHiie which permits the passage of pulses from generator 1 and mykl through element I 35. The second and third pulses of the generator 11 pulses set the second 32 and third 33 D-flip-flops to one state.The third D-flip-flop 33 sets the short-circuited 34 to zero state Fourth pulse generator 11 pulses pass it is through the element And 35 and with its falling edge set to the zero state the first 1) trigger 31.

The series of pulses from the formers of 25 series of pulses of one half of the correctors of each correction block 24 through the fifth element OR 20 are applied to the counter 5, increasing the duration of the clock interval. Series of impulses from formers 25 series

the pulses of the other half of the correctors of each block of 24 corrections are passed through the seventh element 1-ШИ 22 and the fourth element ШШ 19 to the counter 55 reducing the duration of the clock interval. The shapers of 25 seconds limp through the sixth element OR 21 also affect the fourth ton L1Gger 18, which, with the new elements AND 28, prohibits the correctness of the clock interval until the next overflow pulse of the counter 5.

Counter 5 continues counting the inanses arriving from the impulse generator 1: e, and after a predetermined time interval from the moment it overflows, an additional decoder 17 triggers, which through the second element SH 7 confirms the single state of the first trigger 9 and establishes - the state of the second trigger 10, the latter prohibits the passage of the source 2 through the first element And 1 clock pulses of the source 2 until the next operation of the decoder 13. At the same time, (1 pin) 2 sign of the end of the information is set to zero The first state of the trigger 9, which prohibits the flow of pulses from the generator 1 pulses through the second element And b and the fourth element OR 19 to the counter 5, stopping the operation of the device.

F o rmu l invention

1. A device for restoring the measured clock pulses with: Od5; This is the first AND element connected by the first input to the output of the clock pulse pattern and connected to the first input of the first ICH element connected to the first inlet: Ode with the output of the sign of the beginning of information and connected by the output to the input of the logical zero meter installation and to the first input of the second OR element, connected by the output to the inputs of the installation unit, the first and second triggers, the second AND element, but not first and second inputs to the first output of the pulse generator, and to the output of the first trigger connected by the input of the logical zero setting to the output of the information end feature generator, the third OR element connected by the output to the output bus of the clock pulses and connected by the first input to the output of the overflow of the counter connected by the outputs of the bits with the inputs of the decoder, the output of which is connected to the input of the logical zero setting of the second flip-flop connected by an inverted output to the second input of the first element AND and pho worlds of information pulses, characterized in that, in order to improve the accuracy of recovery of reproduced clock pulses, a third Trigger is inserted into it, connected by a logical unit installation input to a decoder output, an additional decoder connected between the outputs of the counter bits and the second input of the second NLI element, the fourth trigger, connected by the installation input of the logical unit to the overflow output of the counter, the fourth element OR, the sub25 of the seventh element OR are connected by the output buses of the form Owners of a series of pulses of the other half of the rectors of each correction unit 2. Device pop, 1, ex

connected by the first input to the output of the second element AND and connected by the output to the summing input of the counter, the fifth element OR, connected by the output so that each house with the subtracting input of the counter, the sixth element OR, connected by the first input to the output of the first AND element, the third element And, the subcontractor of the series of pulses of the correction unit corrector pulse contains the first, second and third D-flip-flop connected by synchronizing

output to the second input is third--, inputs to the first input bus, RS of its OR element, seventh OR element, connected by an output to the second input of the sixth OR element and to the second input of the fourth OR element, and correction blocks, each of which is 0 correctors consisting of impulse series formers connected by the first input buses to the second output of the pulse generator, and from successively connected decoders connected by inputs to the output of the counter digits m and the elements I, and the sixth element OR is connected by a third input to the output of the p element Q

a trigger connected by the input of a set of logic units to the second input bus, and an element And connected by an output to an output bus, and the output of the RS flip-flop is connected to the information input of the first D-flip-flop connected by a direct output to the first input of the element And and. the information input of the second D-flip-flop, the direct output of which is connected to the information input of the third D-trigger connected by the inverse of you

t G-stroke with the installation input zero RS-trigger, and the second input of the element And connected to the first input bus.

This OR is connected by an output to an input of a logical zero installation of the fourth trigger connected by an output to the first inputs of the elements AND correctors of correction blocks, the output of the first element I is connected to the first input of the third element AND connected by a second input to the output

the third trigger, the input of the logical zero setting of which is connected to the overflow output of the counter, the second inputs of the elements AND correctors, each correction unit is connected to the output of one of the information pulse drivers, the output of the element And each offset corrector is connected to the second input bus of one of the series drivers pulses, inputs of that element OR are connected to the output buses of the formers of a series of pulses of one half of the correctors of each correction unit, and inputs

the seventh OR element is connected to the output tires of the pulse shaper series of the other half of the correctors of each correction block. 2. Device pop, 1, characterized in that each

each of them

the driver of the series of pulses of the corrector of the correction unit contains the first, second and third D-flip-flops connected by synchronizing

a trigger connected by a logical unit installation input to a second input bus, and an element connected by an output to an output bus, the output of an RS flip-flop connected to the information input of the first D-trigger connected to a direct output and the first input of the element And. the second D-flip-flop, the direct output of which is connected to the information input of the third D- trigger connected by an inverse L-stroke to the input of the zero setting of the RS flip-flop, and the second input of the And element is connected to the first input bus.

35

thirty

Editor V. Petrash

Compiled by Y. Rosenkrantz

Tehred M. Hodankch Proofreader I. Muska

Order 3710/51 Circulation 543 Subscription

VNIIGM USSR State Committee

for inventions and openings 113035, Moscow, Zh-35, Raushsk nab, d.4 / 5

Production and printing company, Uzhgorod, ul. Project, 4

FIG. 2

Claims (2)

Claim 1. A device for restoring reproduced clock pulses, comprising a first AND element connected by a first input to an output of a clock source and connected by: an output to a first input of a first OR element connected by a second input to an output of a driver of a sign of information beginning and connected by an output to a logic zero setting input counter and to the first input of the second OR element, connected by the output to the inputs of the installation of the logical unit of the first and second triggers, the second AND element, connected to vym and second inputs to first output of the pulse generator. and to the output of the first trigger connected by the logic zero setting input to the output of the end of information indicator driver, the third OR element, connected by the output to the clock output bus and connected by the first input to the Counter Overflow output | connected by the discharge outputs to the decoder inputs, the output of which is connected to the input of the logical zero setting of the second trigger connected by an inverse output to the second input of the first element And, and pulse shapers of information, characterized in that, with the aim of To improve the accuracy of 15 reconstruction of reproduced clock pulses, a third trigger is connected to it, connected to the logic unit setting input with the decoder output, an additional decoder 20 connected between the outputs of the bits of the counter and the second input of the second OR element, the fourth trigger connected to the logical unit setting input to the counter overflow output 25, the fourth OR element connected by the first input to the output of the second AND element and connected by the output to the totalizing counter input, the fifth element OR / connected exit ₃₀ house with a subtracting counter input, the sixth OR element, connected by the first input to the output of the first AND element, the third AND element, connected by the output to the second input of the third-35 of its OR element, the seventh OR element, connected by the output to the second input of the sixth OR element and to the second input of the fourth OR element, and correction units, each of which ₄ θ, are made in the form of correctors consisting of shapers of a series of pulses connected by the first input buses to the second output of the pulse generator, and from connected of 45 sequentially decoders connected by inputs to the outputs of the bits of the counter, and AND elements, the sixth OR element connected by the third input to the output of the fifth OR element and connected by the output to the logic zero input of the fourth trigger connected by output 5 to the first the inputs of the elements And the corrector of the correction blocks, the output of the first element And is connected to the first input of the third element And, connected by the second input to the output of the third trigger, the input of setting a logical zero of which is connected to the output the counter, the second inputs of the elements AND correctors - each correction block is connected to the output of one of the pulse shapers of information, the output of the element And of each corrector of the correction blocks is connected to the second input bus of one of the pulse series shapers, the input of the Fifth element OR is connected to the output buses of the series shapers pulses of one half of the correctors of each correction block, and the inputs of the seventh OR element are connected to the output buses of the series of pulse formers of the other half of the correctors oh block correction. 2. The device according to claim 1, characterized in that each shaper of a series of pulses of the corrector of the correction block contains first, second and third D-flip-flops connected by synchronizing inputs to the first input bus, RS trigger connected to the input of the logical unit with the second input bus, and the AND element connected by the output to the output bus, and the RS-trigger output is connected to the information input of the first D-trigger connected by a direct output to the first input of the And element and to the information input of the second D-trigger, the direct output of which It is connected to the information input of the third D ^ flip-flop connected by an inverse output to the zero-setting input of the RS-flip-flop, and the second input of the And element is connected to the first input bus. FIG. 2