SU1226670A1 - Reversible converter of position code to residual class system code - Google Patents

Abstract

The invention relates to computing. The purpose of the invention is to expand the scope of the converter by providing work on arbitrary bases. This is achieved by the fact that the converter containing (n + 1) counters, (ntI) comparison circuit, two AND elements, OR element, trigger additionally contains a subtractor with corresponding links. 1 il ..

Description

The invention relates to the field of computer technology and can be used to interface with devices operating in the residual class system (SOC).

The purpose of the invention is to expand the scope of application by providing work on arbitrary grounds.

The drawing shows a diagram of the reversible converter of the positional code into the code of the system of residual classes.

A reversible converter of the positional code into the code of the system of residual classes contains counters 1 (-1p + (circuits 2, -2,, comparison, element OF, element OR 4, element 5, trigger 6, subtractor 7, input 8 Start, clock input 9, inputs 10-1 On of the bases, input 11 numbers in the position code, input 12 of the range, output 13 numbers in the position code, inputs 14 (-14 and outputs 15, -15 ”numbers in the code of the residual characters system.

The reversible converter of the positional code into the code of the system of residual classes works as follows. In the mode of converting the positional code into the RN code, the counters 1 are reset to zero, the grounds codes p are set at inputs 10. selected SOK, input 11 is the code of the number A to be converted. Trigger 6 is in the zero state. With the arrival of a pulse at input 8, trigger 6 is transferred to a single state and the potential from its direct output allows receipt of clock pulses from input 9 through an AND 5 element to the clock inputs of counters 1. Each of the Ij-lo counters operates modulo p, those. as soon as the contents of the counter are compared with p, the signal from the output of the comparison circuit 2 zeroes the counter 1 As soon as the contents of the counter 1 becomes equal to the number A being converted, the signal from the output of the comparison circuit 2 passes through the element OR 4, sets trigger 6 to the zero state, which will lead to the closure of the element And 5 and will exclude further receipt of clock pulses in the converter. The counters will contain the result of converting the position number A to a SOC.

In the mode of converting numbers from SOC to positional form,

in counters

L recorded to

d residues N, - “, counter. and the trigger 6 is reset, at the inputs 10 the codes of the bases of the selected RCC are set, at the input 12 the number code is set

selected range of ROS. With the arrival of the pulse at the input 8, the Start the contents of the counters Ij-lf, begin to change along

0

five

modules with the initial state ", -c (, and the contents of the counter 1 n, - monotonously grow. As soon as the contents of the counters (in the non-positional representation will be equal to the range of the selected SOC, all circuits 2, -2 comparisons will work, and the output of the multi-input element And 3 wits the signal that passes through the element OR 4, will transfer the trigger 6 to the zero state and thereby stop the flow of clock pulses into the circuit. Since in the counters Ij-lf, the counting is performed, starting from the number A to the range P, then in the counter 1 |, + 1 there is the difference code А Р - A. Sledova Of course, at the moment of the appearance of the signal from the output of the multi-input element And 3, the output of the subtractor 7 contains the code of the transformed number

A P -A

35

Claims (1)

Formula invented and  A reversible converter of a positional code into a code of a system of residual classes containing (n +) counters, n is the number of bases, (n + 1) a comparison circuit, two AND elements, an OR element, a trigger, and the number inputs in the system of residual classes of the converter are connected to information . the inputs of the first n counters, the outputs of which are connected to the first inputs of the respective comparison circuits, the outputs of which are connected to the corresponding inputs of the first an element AND whose output and output (n + 1) -th comparison circuit are connected respectively to the first and second inputs of the OR element, the output of which is connected to the zero input of the trigger, the single input and output of which are connected respectively to the start input of the converter and to the first input of the second element AND, the second input of which is the clock input of the converter, the output of the second element AND is connected to the counting inputs of the counters from the first to (n + 1), output ( The n-and-i-th counter is connected to the first input of the (n + 1) -th comparison circuit, the second input of which is the number input in the position code of the converter, the second inputs of the comparison circuit with the first through the n-th are the inputs of the converter base, meter outputs from first to The nth are outputs of the number in the code of the system of residual classes of the converter, differing Editor A. Sabo Compiled by A. Klyuev Tehred V. Kadar Order 2147/5 Circulation 816 Subscription VNIIPI USSR State Committee for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., 4/5 Production and printing company, Uzhgorod, Projecto st., 4. 26670 the fact that, in order to expand the scope of application by providing work on arbitrary grounds, it contains a subtractor, with the outputs 5 of the comparison circuits with the first through the n-th being connected to the reset inputs of the corresponding counters, the output of the (n + 1) -th the counter, the output of the first element, AND, and the input of the range of numbers of the transformer; T ,, U / S Proof-reader I.Erdeyi