SU1256014A1 - Device for sorting data - Google Patents

Abstract

The invention relates to computing and can be used for processing data arrays. The purpose of the invention is to increase the speed when sorting large data arrays. The device contains number registers, decoders, multi-input elements OR, analog-to-code converters, key groups, two groups of analog adders, delay elements, output registers. The transducer converts input codes into position codes, which are summed on analog adders of the first group. At the outputs of the summers of the second group, voltages are formed corresponding to the number of the number. 1 il. you ate od

Description

The invention relates to computing and can be used for processing data arrays.

The purpose of the invention is to increase the speed of the device when sorting large arrays of numbers.

The device contains the registers of the number 1, decoders 2, multi-input elements 3 OR, analog-code converters 4, key group .5, first group of analog adders 6, second group of analog adders 7, output registers 8, first delay element 9, second delay element 10 , input 11 launch.

The device works as follows.

Registers 1 contain codes of numbers that must be sorted in ascending order. A pulse is applied to the device input 11, which zeros the registers 8 and through delay element 9 gives the resolution to the decoders 2, ..., 1 to convert the binary codes recorded in registers 1 to the codes with base 2 (t is the digit number 1). ). As a result of decoding, each decoder 2, ... 2 has a unit potential that is seen only at one of (2 -1) outputs. These potentials through the elements 3, ..., 3 OR, respectively

but for outputs 1, ..., k, decoders 2, .. ,, 2, are fed to the inputs of analog adders of the first group 6 ,, ..., 6, on which the unit potentials from the outputs of blocks 3 3 su1 are routed,

Denote the output voltage

blocks 3

one

and.

(and.

., J through .j, v.j, is equal to either Uy, or O, U :, is the potential corresponding to unity), on. the outputs of the adders of the first group we get

31

+ and

 32

and

 : one

31

Thus, if there are equal numbers, then the maximum value of the voltage at the outputs of the adders will be equal to n C, and the minimum and.

Voltages from the outputs of the adders 6 | , ..., 6 1 are received respectively at the inputs of the keys 5, ..., 5 groups of keys. One of the keys 5, ...,

5 opens with a single potential from the output of the corresponding decoder (only one key of each group is opened, since a single potential takes place only at one output of each decoder 2, ... 2).

Thus, at the output of the adders of the second group 7,. equal

7 board h

are the voltages equal to the output voltage of the public keys of the group

H

5 and corresponding to the number

numbers For example, the smallest would be U, the next by

the value of 2U.

| | | and the maximum number, if there are no such numbers n and the same, n and. In case there are the same numbers, then the unit potential on the same outputs of the corresponding decoders will open, the same keys of the corresponding switching blocks will open, and the same potentials will be output on the outputs of the corresponding adders of the second group.

Starting impulse after passing -,. neither through the delay blocks 2 and 10 enters the permitting inputs of analog-code converters 4, ..., 4, (as such converters it is necessary to use analog-to-digital read converters that carried out an up-conversion in one cycle), voltage at the inputs of the blocks 4, ,,,, 4 are converted into codes, corresponding to the appropriate number, and the numbers of the numbers that are written into registers 8.

Claims (1)

Invention Formula A device for data sorting, containing decoders, k.1 multi-input elements OR (k 2 -1, m number of numbers), output registers, number registers, whose outputs connected to the information inputs of the corresponding decoders, characterized in that, in order to increase speed when sorting large arrays of numbers, it introduces two delay elements, two groups of analog adders, h groups of keys to keys in each group, and analog-code converters, with the device start input connected to the installation input,. to the zero state of the output registers, through the first delay element with the enable inputs of the decoders and through the second delay element - from the enable inputs of analog-to-code converters, the I -e outputs of the decoders (i 1, k) are connected to the inputs tx of the STI elements, the output of each f -ro element OR is connected to the {-th inputs jX of analog adders of the first group (. I,. .., (C), the output of each i-th analog adder of the first group is connected to information inputs (-X keys of each group The inputs whose control inputs are connected to the outputs of the corresponding decoders, the outputs of the keys of each group are connected to the inputs of the corresponding analog adders of the second group, the outputs of which are connected to the inputs of the corresponding analog-code converters, the outputs of which are connected to the information inputs of the corresponding output registers. Editor P.Kossey Order 4824/48 Tehred L. Sergdakova Circulation 671 VNSPI State Committee of the USSR for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nar., d. Production and printing company, Uzhgorod, Projecto st., 4 Proofreader A.Obruchar Subscription