SU1185546A1 - One-channel digital device for pulse-phase controlling of rectifier converter - Google Patents

Abstract

A SINGLE-CHANNEL DIGITAL DEVICE FOR PULSED-PHASE CONTROL OF A VENTIAL INVERTER, containing a synchronization unit, a regular phase determination unit, the inputs of which are from the first to the fifth, where the power circuit is phased, are connected to the corresponding outputs of the unit. synchronization, synchronized with the network, a pulse generator, which includes a counter and a phase detector connected in series, the first input of which is connected to the output of the high discharge of the counter, and the second input to one of the outputs of the synchronization unit, low frequency generator and voltage controlled generator the output of which is connected to the counter input of the counter, the comparison unit, the first input of which is connected to the input control bus of the device, and the block for the distribution and generation of unlocked pulses, information Its input is connected to the output of the comparator unit, and each control input from the first to the fifth with the corresponding output of the next phase determination unit, characterized in that, in order to simplify the device and increase the linearity of the decoder characteristic, it is equipped with a long-term memory unit programmed in accordance with a given control law, the address input of which is its S most significant bits, where S is the size of the n-1 number in the applied code, directly or through a unitary converter the code into a parallel numeric code is connected to the outputs of the next phase determination unit, and the remaining bits are connected to the output of a counter that is part of a pulse generator synchronized with the network, the second input of the comparison unit 00 is connected to the output of the amp &; 1 long-term memory, and the block of distribution and formation of unlocking of the operating pulses is provided with additional n outputs, each of which is connected to one of the inputs from P + 1-GO to 2n-th block of determining the next phase and additional control power inputs, each of which is connected to one of the outputs of the synchronization unit, while the next phase determination unit contains n triggers, n I elements and a presetter, the first input of each i-ro trigger is connected to the i-th input of the

Description

phase, the second input of each 1st flip-flop is connected to the n + 1-th input of the regular phase determining unit, the first input of each i-ro element I is connected to the forward output of the 1st flip-flop, the second input is connected to the inverse trigger output numbered i - 1 + gn, where

1 with i 1

and the output is connected Oh when i e 1

to the 1st output of the next phase determination unit, one of the inputs of each trigger is intermediate with the output of the presetting unit.

one

The invention relates to converter equipment, namely, devices designed to control the switching angle of high-power valve converters.

FIG. 1 shows a diagram of a single-channel digital device for pulse-phase control of a valve converter; in fig. 2 is a block diagram for determining the next phase.

The device comprises a synchronization unit 1, a regular phase determination unit 2, a 3 pulse generator synchronized with the network, a distribution and forming unit for trigger pulses 4, a unitary code-to-parallel numerical code converter 5, a non-volatile memory unit 6 and a comparison unit 7. The 3-pulse synchronized with the generator network includes a phase detector 8, a low-pass filter 9, a voltage-controlled oscillator 10 and a counter 11,

The block 2 for determining the next phase contains n triggers 12, n elements I 13 and a presetting unit 14.

The device works as follows.

The phase locked loop of the pulse generator 3 synchronized with the network provides the generator frequency 10 such that the signal at the output of the higher bit of counter 11 in frequency and phase coincides with the anode voltage of one of the gates, for example, first. The code in the counter 11 at any time moment with some precision of discretization is proportional to the phase of the anode voltage2

neither this valve. The next phase determination unit 2 selects a signal at one of its outputs, and the number of this output coincides with the number of the next phase. Thus, at the outputs of block 2, the unitary code of the number of the next phase is allocated, which is converted by block 5 into a parallel numerical code. Block 6 of the long-term memory converts the phase code of the anode voltage of one of the valves, for example, the first, and the next phase number into a spreading reference code proportional to the phase wt with some accuracy; anode voltage of the next valve or some of its functions, for example, cos wt. When the sweep code reaches the value set at the control input of the device, the comparison unit 7 is activated and a unlocking pulse is sent to one of the device outputs, and the state of the next phase determination unit 2 also changes. Each trigger 12 (Fig. 2) is established by a pulse of the synchronization unit 1 at the moment of natural unlocking of the valve of the corresponding phase and triggered by a pulse of the distribution unit 4 and the formation of the triggering pulses during the activation of the triggering pulse on the control electrode of this valve. The signal is present at any output of block 2 when the corresponding phase is regular. Preset unit 14 resets all triggers when the power is turned on.

Thus, in the proposed (the Device, the calculation of the reference code is performed in a tabular manner. The non-volatile memory unit 6 is programmed so that the necessary reference code is stored in each memory cell, which is a function of two arguments, namely the code in the counter 11 and the next phase number , the aggregate of which is the address of this cell. If the block 6 of non-volatile memory contains n identical nodes, with 464 than the sampling of memory areas is carried out by initiating one of them without decrypting its number, the older rows address bus unit 6 may be directly to the outputs podklyu1cheny unit 2 for determining the next phase. In this case, the converter 5 to parallel unitary numeric code excluded from. the device circuit.

Fa & .2

Claims (1)

A SINGLE-CHANNEL DIGITAL DEVICE FOR PULSE-PHASE CONTROL OF A VALVE CONVERTER, containing a synchronization unit, a unit for determining the next phase, the inputs of which are from the first to the nth, where η is the phase diagram of the power circuit connected to the corresponding outputs of the unit. synchronization, a pulse generator synchronized with the network, which includes a counter and a series-connected phase detector, the first input of which is connected to the output of the highest level of the counter, and the second input - to one of the outputs of the synchronization unit, a low-pass filter and a voltage-controlled generator, the output of which connected to the counter input of the counter, a comparison unit, the first input of which is connected to the input control bus of the device, and a block for the distribution and generation of unlocking pulses, information input which is connected to the output of the comparison unit, and each control input from the first to the fifth with the corresponding output of the next phase determination unit, characterized in that, in order to simplify the device and increase the linearity of the output characteristic of the converter, it is equipped with a long-term memory unit programmed in accordance with with a given control law, whose address input is its S high-order bits, where S is the bit capacity of the number p-1 in the applied code, directly or through a unitary code converter in parallel an integer numerical code is connected to the outputs of the next phase determination unit, and the remaining bits are bitwise connected to the output of the counter, which is part of the pulse generator synchronized with the network, the second input of the comparison unit is bitwise connected to the output of the long-term memory block, and the block for the distribution and generation of unlocking pulses is equipped with additional η outputs, each of which is connected to one of the inputs n + 1 through 2 of the second block for determining the next phase and additional η control inputs, each of which x is connected to one of the outputs of synchronizing unit, wherein the determination unit comprises another phase triggers η, η elements D and the preset node, the first input of each i-ro trigger connected to the i-th entry unit determining oche ate ate About the rare phase, the second input of each i-th trigger is connected to the n + 1-th input of the next phase detection unit, the first input of each i-ro element And is connected to the direct output of the i-ro trigger, the second input is connected to the inverse output of the trigger with the number i - 1 + gn, where g = _. ,,. and an output connected at ^s 0 1 r 1 to the i-th output block determining another phase, one of the inputs of each flip-flop with the median output node presetter.