SU1013944A1 - Number comparison device - Google Patents

Abstract

A DEVICE FOR COMPARISON OF NUMBERS, containing n porazdnyh cells of comparison, elements AND, OR, NOT, and the first output of each i-th porazrah of the cell of comparison, where i 1, 2, ... (p-1) is connected to the first input of the () -th one bit comparison cell, the second outputs of all bitwise comparison cells and the third outputs of all but the first cell are connected to the corresponding inputs of the OR element, the output of which is connected to the first the output of the device and through the first element is NOT - with the first input of the element. And, the output of which is the second output of the device, the first output of the nth bit of the comparison cell is connected. with the input of the second element NOT, the second input of each j-th bit of the comparison cell is connected to the input of the direct value of the j-ro digit of the first device number (j 2,3 ... n), the first and second inputs of the first cell are connected respectively the inputs of the direct and inverse values of the first digit of the first number of the device, the third and fourth inputs of the first cell are connected respectively to the inputs of the direct and inverse values of the first digit of the second number of the device, the third and fourth inputs of each j-th random cell of the comparison are connected with the inputs of the direct and inverse values of the j-ro of the second number of the device, respectively; the fourth output of the jth bit of a comparison cell; it is connected to the fifth input (3 - 1) of the bit of a comparison cell, the sixth input of each j the th bit of the comparison cell is connected to the first control input of the representation of the codes of the device numbers being compared, the fifth input of the second comparison cell is connected to the direct value of the first digit of the first number of the device, the first bit of the comparison cell contains the elements AND, OR, the first and secondthe cell outputs are connected to the first inputs of the first and second And elements, respectively, and the third and fourth inputs are connected to the second inputs of the second (the first and the first And elements, respectively, and the KOTopi X outputs are connected to the element inputs silt; -, the output of the first element And Connected to the second output of the cell ,, S The subsequent comparison cells contain: - the elements AND, OR, HEj, a half adder, the first input of the cell connected to the first inputs of the first and second elements AND, the second input of the cell connected to the first entrance 00 of the half adder and the first input tre; o t And, the outputs of the first and second elements of AND are the second eye and the third output of the co4 cell, responsibly, the output of the half adder is connected to the fourth output of the cell, the fourth input of the cell is connected to the second input of the second element I, the output of the third element I is connected to the first input of the element OR, the sixth input of the cell is connected to the first input of the fourth element AND, characterized in that, in order to expand the scope. By comparing two numbers represented in different codes, it contains additional elements NOT, with the first input

Description

The representation of the codes of compared numbers of the device is connected to the input of the first element NOT, the output of which is connected to the seventh and the inputs of -scex random comparison cells, except for the first, the second input of the control representing the codes of the compared numbers of the device is connected to the eighth and In addition, in addition to the first, the first output of the nth bit of the comparison reference cell is connected to the third output of the device, the output of the second element is NOT connected to the second input of the element a AND, the first bit cell of the comparison cell additionally contains the element NOT, the input of which is connected to the output of the OR cell, and the output is the first cell output, je bitwise comparison cell (j 2,3 ... n) additionally contains a controlling half-adder, with the first entry

the control half-adder is connected to the third input of the cell, and the second input is connected to the output of the OR element and the third input of the second element AND, the fourth input of which is connected to the ninth input of the cell, the second input of the OR element is connected to the output of the fourth element AND, the second input of which is connected to the output of the half adder, the second input of the first element I and the fourth output of the cell, the output of the controlling half adder is connected to the input of the element NOT and the third input of the first element I, the fourth input of which is connected to the eighth input of the cell The second input of the half adder is connected to the fifth input of the cell, the output of the element is NOT connected to the first input of the fifth element And, the second input of which is connected to the first input of the first element: that And, and the output is connected to the first output of the cell, the second input of the third element And is connected to the seventh entrance of the cell.

t,

The invention relates to computing and can be used in automation devices and discrete technology.

Devices are known that allow numbers to be compared, both of which are represented in binary code or in Gre code.

The disadvantage of this device is that in order to function correctly it requires distribution polling pulses, which complicates the device.

The closest to the present invention is a device for comparing numbers, containing n bitwise comparison cells, elements AND, OR, NOT, and the first output of each i-th bit memory comparison cell, where i 1, 2, .... (iv 1 ), is connected to the first input () of the first comparison cell, the second outputs of all but the first one are connected to the corresponding inputs of the OR element, the output of which is connected to the first output of the device and through the first element NOT to the first input of the AND element, output which is the first exit of the device, the first exit is nth time The reference comparison cell is connected to the input of the second element NOT; the second input of each jth bit comparison cell is connected to the input of the direct value of the jth digit of the first steady state number

(J 2,3, ... p), the first and second inputs of the first cell are connected respectively to the inputs of the direct and inverse values of the first bit of the first number of the device, and the third and fourth inputs of the first, cells are connected respectively to the inputs of the direct and inverse the first bit values of the second device number, the third and fourth inputs of each jth bit comparison cell are connected to the inputs of the direct and inverse values of the second j number of the second number respectively

5 devices, fourth exit jth

the comparison bit cell is connected to the fifth input, (J + 1) -th bit cell, the sixth input of each jth bit cell is connected to the first control input. codes of the device numbers being compared, the fifth input of the second comparison cell is connected to the direct value of the first digit of the first number, the device, the first output of the 5th bit comparison cell is connected to the second input of the AND element, the output of the second element is NOT the third output of the device , the first bit of the comparison cell contains AND, OR elements, the first and second inputs of the cell being connected to the first inputs of the first and second AND elements, respectively, and the third and fourth - to the second inputs of the second and first go

AND elements, the outputs of which are connected to the inputs of the OR element, the output of the first element AND is connected to the second output of the cell, the following: the comparison cells contain the AND, OR, NOT elements, a half-adder, the first input of the cell is connected to the input of the first element and the first input of the OR element , the first and second inputs of the first element I are connected to the second and fourth inputs of the cell, and the output is connected to the second input of the element NOT and the first input of the second element I whose output is connected to the second output of the cell, the second input of the second element I connected with the output of the second element is NOT, and the third with the output of the first element is NOT and the first input of the third element is And, the second input of which is connected to the output of the fourth element AND and the third input of the element OR, the third input of the third element And is connected to the first input of the half adder, the input of the second element NOT and the output of the fifth element I, the first and second inputs of the fourth element I are connected to the third and fifth inputs of the cell, the output of the element OR is connected to the first output of the cell, the output of the third element I is connected to the third output of the Cell, the first input d fifth AND gate connected to the seventh input of the cell, and the second - sixth input cell, the second input of the half-adder connected to the first input of the first AND gate, the half-adder output is connected to the fourth output of cell 2.

A disadvantage of the known device is the impossibility of comparing numbers represented by different codes.

The aim of the invention is to expand the field of application of the device by comparing two numbers represented in different codes. The goal is achieved by the fact that a device for comparing numbers, containing n bitwise comparison cells, the elements OR, AND, NOT, and the first output of each i-th bit memory of the comparison cell, where i 1,2 ,, .. (. 1), connected to the first input (1 + 1) -th bit comparison check, the second outputs of all bit comparison cells and third and all outputs, except the first, are connected to the corresponding inputs of the OR element, the output of which is connected to the first output device and through the first element is NOT with the first input of the element AND, the output of which is w By the output of the device, the first output of the nth bit cell of the comparison is. so, the input of the second element is NOT, the second input of each j-th bit cell of the comparison cell is connected to the input of the direct value of the j-ro digit of the first device number (j 2,3 ... n), the first and second inputs of the first cell are connected respectively with the inputs of the direct and inverse values of the first bit of the first device number, the third and fourth inputs of the first cell are connected respectively to the inputs of the direct and inverse values of the first bit of the second number of the device, the third and fourth inputs of each j-th bit cell of the comparison cell are connected to in rows, respectively, the forward and inverse values of j-ro discharge of the second device, the fourth output j-th. the bit comparison cell is connected to the fifth input of the (j + 1) -th bit comparison cell, the sixth input of each jth bit comparison cell is connected to the first control input of the representation of the numbers of the device being compared, the fifth input of the second comparison cell is connected with the direct value of the first bit of the first number of the device, the first bit of the comparison cell contains the elements AND, OR, the first and second inputs of the cell are connected to the first inputs of the first and second elements respectively, and the third and fourth inputs are from the second inputs, respectively, of the second and first elements AND, whose outputs are connected to the inputs of the OR element, the output of the first element AND are connected to the second output of the cell, the subsequent comparison cells contain the AND, OR, NOT elements, a half adder, the first input of the cell connected to the first inputs of the first and the second element and the second input of the cell is connected to the first input of the half adder and the first input of the third element I, the outputs of the first and

5 of the second AND elements are the second and third cell outputs, respectively, the output of the half adder connects to the fourth output of the cell, the fourth input of the cell is connected to the second input of the second element AND the output of the third element I connected to the first input of the OR element, neck. This cell input is connected to the first input of the fourth element AND, co5 holds additional elements NOT, the first control input representing the codes of the compared numbers of the device connected to the input of the first element NOT whose output

0 is connected to the seventh inputs of all bitwise comparison cells, except the first, the second input controls the presentation of the codes of the compared numbers. device is connected to the eighth and through the second additional element

five

HE - with nine inputs of all random comparison cells, except for the first one, the first output of the nth random memory of the comparison cell is connected to the third output of the device, the output of the second element is NOT connected to the second input of the AND element, the first random cell of the comparison additionally contains the element whose input is connected to the output of the OR element, and the output is the first output of the cell, -je serial comparison cells (J 2,3 ... n) additionally contain a control half-accumulator, and the first input of the control half-adder is connected to the third input m cell, and the second input is the output of the OR element and the third input of the second element AND, the fourth input of which is connected to the ninth input of the cell, the second input of the OR element is connected to the output of the fourth AND element, the second input of which is connected to the output of the half adder, the second input The first element Y and the fourth output of the cell, the output of the controlling half-1V | ator is connected to the input of the element NOT and the third input of the first element I, the fourth input of which is connected to the eighth input of the cell, the second input of the half-adder is connected to the fifth input Menus, the output element is coupled to the first input of the fifth AND gate, a second .The inputs coupled to a first input of the first AND gate and the output of the first output cell, a second input of the third AND element is connected to a seventh yhodom cell.

The drawing shows a functional diagram of the device.

The device contains bit cells of comparison 1, which consist of elements AND 2 and 3, element OR 4, element NOT 5, half-combinators b and 7, elements AND 8-12, element NOT 13, element OR 14, elements 15 18, element OR 19, element AND 20, control buses 21 and 22, and output tires 23-25.

The device operates in three modes selected by supplying a single potential to control bus 24 or 25 and presented in the table.

Gre

Gre

Binary

In all three modes of operation of the first bit size, the comparison cell works as follows.

If the higher bits of the numbers being compared are not equal, then at the output of the element OR 4, the element AND 2 or AND 3, cell 1, there appears a single potential that is inverted by the element NOT 5. In both cases, the elements AND 10-12 are second whose-

Comparison cells are closed with a zero potential from the output of the element HE 5, and elements AND 10-12 of all subsequent bit-comparison cells are closed with zero potential from the outputs

element 10. At ab, (where a and b are bit values), a unit appears at the output of element 3, which through the element OR 19 appears on the output bus 23 (A B).

With a b from the output busbars 23 and 25, a zero potential is removed, and one is removed from the bus 24 (A B). In the event that, at the output of the HE i i5 elements of the highest cell, there remains a unit that unlocks the AND 10-12 elements of the second bit of the comparison cell.

The operation of the second bit cell of the comparison is determined by the mode of operation and is resolved by the unit potential supplied to the inputs of the AND 10-12 elements from the output of the highest bit cell of the comparison {a. B.

In the comparison mode of two numbers represented by the Gre codes, the unit potential applied to the control bus 22 unlocks the AND 11 elements and through the NOT 16 element locks the AND 12 elements of all the comparison cells. In other modes

work items And 11 are locked, and items And 12 are unlocked.

The work of the second porous chey-. ki comparison and the entire device "as a whole in the mode of comparing two numbers

represented by binary codes, happens as follows.

. In this mode, the potential is determined by the value of a.2, through the open element I 9 and further through the element

OR 14 enters the inputs of the element And 12 and half adder 6. In case a 2 b, / from the output of half adder b to the input of the element NOT 13 is post-. There is no potential. Unit

the potential from the output of the element HE 13 through the open element I 10 (a b) permits the comparison in the following. See the same cell in comparison. At the same time, at the output of the element And 12, there remains a zero potential, since the values a, 2 and b 2 arrive at its inputs. In the case a, b, b, the output of the half-adder b is removed, the unit potential that arrives is not

the input element is NOT 13. The zero potential from the output of the element NO 13 through the elements And 10 forbids the comparison in all subsequent bits and the zero potential will be on the output bus 25 (A B). When a b2, all potentials of the And 12 element are unit potentials. The unit from the output of the element AND 12 through the element OR 19 appears on the output bus 23 (A B). If the output is 23 and 25, the potentials are zero. In this case, from the output of the element I 20 to the output bus 24 (A B), a single potential flows. The remaining bit comparison cells work in the same way. In the comparison mode of two numbers represented by A - the Gre code, B is a binary code, the second bit of the comparison cell works as follows. A single potential applied to bus 21 unlocks the elements of AND 8, and the zero potential from the output of the element NOT 15 locks the elements of AND 9. At the same time, the value of a in the binary code from the output of the half-adder 7 through the open element AND 8, the element OR 14 goes to the inputs of the element I, 12 and the half adder 6. Further, the work of the cell and the comparison device as a whole occurs similarly to the operation of the device in the comparison mode of two numbers, represented by binary codes, starting from the moment the value arrives at the inputs of the half adder 6 and the element 12 set up va mode comparing two numbers represented by a Gray code, is as follows. - In this case, the value of a through the open element AND 9, the element OR 14 enters the input of the half adder 6. If a2 b, the zero potential from the output of the half adder 6 blocks the element 11 and the unit potential C of the element HE 13 through the open element 10 allows the comparison in the next cell comparison. If 2 2 unit potential from the output of the half-supermator 6 unlocks the element 11 and the zero potential from the output of the element is NOT 13 through the element 10 and prohibits comparison in subsequent bit-wise comparison cells. The result of the comparison depends on the parity signal from the outputs of the half adders 7. The remaining bit comparison cells work similarly. Thus, the proposed device is multifunctional and can make comparisons of numbers represented by binary codgs "and Gre codes, as well as a comparison of two numbers if the number A is represented in the Gre code and the B number in the binary code. The proposed device allows | to compare two numbers with different codes without additional code conversion.

Claims (1)

DEVICE FOR COMPARING NUMBERS, containing η bitwise comparison cells, AND, OR, NOT elements, the first output of each i-th bit of the comparison cell, where i = 1, 2 (and-1 is connected to the first input of the (1 + 1) -th bit * comparison cells, the second outputs of all bitwise comparison cells and the third outputs of all but the first cell are connected to the corresponding inputs of the OR element, the output of which is connected to the first output of the device and through the first element NOT to the first input of the AND element, the output of which is the second output of the device, the first output of the nth the bit of the comparison cell is connected to the input of the second element NOT, the second input of each j-th bit of the cell of comparison is connected to the input of the direct value j-ro of the discharge of the first · number of the device (j = 2,3 ... η), the first and second inputs of the first the cells are connected respectively to the inputs of the direct and inverse values of the first discharge of the first number of the device, the third and fourth inputs of the first cell are connected, respectively, to the inputs of the direct and inverse values of the first discharge of the second number of the device, the third and fourth inputs of each jth bit of the comparison cell are connected to the inputs of the direct and inverse values of the j-ro discharge of the second device number, the fourth output of the jth bit of the comparison cell is connected to the fifth input of the (j + 1) -fi bit of the comparison cell, the sixth input of each jth bit the comparison cell is connected to the first input of the representation control of the codes of the compared numbers of the device, the fifth input of the second comparison cell is connected to the direct value of the first bit of the first number of the device, the first bit of the comparison cell contains the elements AND, OR, p why does the first and second output of the cell are connected to the first inputs of the first and second elements of And, respectively, and the third and fourth inputs to the second inputs of the second and the first elements of And, the output of κοτορι х are connected to the inputs of the IL element? ·, the output of the first AND element It is connected to the second output of the cell, the subsequent comparison cells contain elements. AND, OR, NOT> a half-adder, with the first input of the cell being connected to the first inputs of the first and second elements And, the second input of the cell is connected to the first input of the half-adder and the first input m of the third element And, the outputs of the first and second elements And are the second and third outputs of the cell, respectively, the output of the half-adder is connected to the fourth-output of the cell, the fourth input of the cell is connected to the second input of the second element And, the output of the third element And connect. yen with the first input of the OR element, the sixth input of the cell is connected, with the first input of the fourth AND element, characterized in that, in order to expand the area. application by comparing the two numbers represented in different codes, it contains additional NOT elements, and the first input the control by the representation of codes of the compared numbers of the device is connected to the input of the first element NOT, the output of which is connected to the seventh and the inputs of all bitwise comparison cells, except the first, the second input of the control of the representation of codes of the compared numbers l of the device is connected to the eighth and through the second additional element NOT to the ninth inputs of all bitwise comparison cells, except for the first one, the first output of the nth bit bit comparison cell is connected to the third output of the device, the output of the second element is NOT connected to the second input of the And element, the first bit the comparison cell additionally contains an element NOT whose input is connected to the output of the OR element, and the output is the first output of the cell, je bitwise comparison cells (j = 2,3 ... η) additionally contain a control half-adder, The first input of the control half-adder is connected to the third input of the cell, and the second input to the output of the OR element and the third input of the second AND element, the fourth input of which is connected to the ninth input of the cell, the second input of the OR element is connected to the output of the fourth AND element, the second input of which is connected with the output of the half-adder, the second input of the first element And and the fourth output of the cell, the output of the control half-adder is connected to the input of the element NOT and the third input of the first element And, the fourth input of which is connected to the eighth input m of the cell, the second input of the half-adder is connected to the fifth input of the cell, the output of the element is NOT connected to the first input of the fifth element And, the second input of which is connected to the first input of the first element And, the output is connected to the first output of the cell, the second input of the third element And is connected to the seventh cell entry. 1 .