SU1001534A1 - Rate scaler with variable countdown ratio - Google Patents

Description

(54) DIVIDER OF FREQUENCY OF INVESTIGATION AND LIPULS WITH VARIABLE DIVISION FACTOR

one

The invention relates to a pulse technique and can be used in automation and computer systems.

A pulse frequency divider is known, comprising a C-bit binary pulse counter, including a buffer register connected to the output of a delay element, whose input is connected to a pulse generator, and an information register connected to a delay, whose input is connected to a pulse generator, transfer and input valves, AND, OR, NOT elements, input buses of the whole and fractional parts of the division factor, one-bit binary counter lj.

A disadvantage of the known device is structural bulkiness.

The closest to the proposed technical entity is a pulse frequency divider with a fractional variable division factor, containing a pulse generator connected to the input of the phase shifting element, which by its outputs is connected to the first inputs of the first and second coincidence units connected to the outputs the inputs of the first and second

5 OR elements, respectively, a switch connected by inputs to the outputs of the memory register of the fractional part of the coefficient, whose information inputs are part of the fractional part

° factor, and the control input is connected to the output bus, the control inputs of the shift register and the counter, as well as the input of the delay element, the outputs of the switch with the second

 the inputs of the first and second blocks of coincidence, the AND-discharge counter, the setting inputs of which are connected to the stitches of recording the whole part, the coefficient, the outputs with the AND element whose output is connected

20 with the first input of the first trigger, the second input of which is connected to the output of the second element I, the direct output to the first input of the third element I, and 16 the inverse output to the second input of the second trigger, the first input of which is connected to the output of the third element AND output bus and the output with the first input of the second element And, the second input of which through the inverter is connected to the output of the second element OR and the second input of the third element And, and the third input to the first input of the fifth element I. And the second output of the shift register, the second output of which It is connected to the first input of the fourth element I, the first block of which is connected to the output of the delay element and output to the clock input of the switch, while the second input of the fifth element AND is connected to the output of the first element OR, and the output to the counter input 231, However The known frequency divider has a large amount of equipment and not enough high speed. The purpose of the invention is to increase the speed of action while simplifying the device. The goal is achieved by the fact that in the pulse frequency divider with a variable division ratio of the Sawyer ;; 1K.y generator npupsy, output: 70voro soadinya about the second phase shift of ushego c- ej: Ae :: jras elzglenty I, counting imp ;; t: o: i; h ,, pa p two outputs with co: -Hestzzuk a) shkim vkodami kkrvsd-; 1 lamment and treger, her: x & isepBt ro. h cohort; with dervp and p.7ksv;.,; and correspondingly - second ji third elements and elements, elements. OR, in the form of ve ;; til and form 1 rovg, spruce: Cls pulsoz5 peray and second inputs of the x cgrDDiiiiesiesii with outputs corresponding to n:; ; - on the third and third-party, and with the v-th v, ;;. uuOfv5 valve, pears of the inlets: sdklkhachka to the installation bus of the whole JBOIH, n the first in the code / four-way and the second, and the second input of the D D: and: : Lugochen to the installation bus code Fractional part, and the output - to the entrance of the third Grngger, the direct output of which Ooednken with the first inputs of the fifth and Xyesuy elamentov I, and inverse you ) Soda with the first inputs of the seventh and eighth Elamaates And, the second inputs of the x with the inverse input of the Fourth trigger, the direct No. 1 code which is connected to the first input of the first I.Pemeet OR, the output of which is connected to the 6th input of the counter, pulses, and the second IJod. With the first output of the first trigger, the xer-output of which is connected by the second inputs of the fifth and sixth K44 elements, the direct outputs of the sixth and eighth elements of And are connected to the first inputs of the first and second triggers, and the inverse of the third inputs, respectively P addition to the seventh elements And, outputs ko. The second inputs are connected to the first inputs of the fourth and fifth triggers, the second input of which is connected to the first output of the valve, the group of outputs of which is connected to the installation inputs of the pulse counter, the third input of the fourth trigger is connected to the output of the pulse generator, the second input of the first trigger and the second input of the third element And, and the third input of the fifth trigger is connected to the second input of the second element I, the output of the phase-shifting element and the second input of the second trigger, the third input of which is connected to the output of the third element And the one and the first input of the second OR gate, a second input coupled to an output of the second AND gate and a third input of the first flip-flop, wherein the third inputs of the sixth and eighth AND gates connected to the output of the first item I. In FIG. 1 shows the structure of the proposed device; on phage. 2 temporary diagrams, on sn kkh: s-Tye eggch: work. The service includes generator 1 and jrtymiCDE, triggers 2-6, phase shift element element 7., vector 8, elements 9-16, Yarova forms Tejsb 17 write pulses, elements OR 18- and 19, counter 20 pulses, recalculate block 21, bus 22 installation code of the whole part, bus 23 installation code fractional part. Phasos-Zekg-ayuigay element is a delay time equal to 8.5 periods of the clock frequency, Recalculate block 21 consists of a BDro bit performed on trigger 5 in € to the element OR 18, and counter 2C kmul-T : .sov, representing the gnagal (|.-1) bits, made by Ti-a -1) of the TRI1 connected in series; hera; The conversion unit 21 operates in the subtraction p-range. The shaper 1 7 write pulses can be performed on the series-connected element OR, the element of the delay in the element I. The device operates as follows. Depvtel can work in three modes: division into mixed, whole and fractional numbers, multiples of 0.5. 510 For dividing by a mixed number, it is necessary to send 22 the code for the whole part of the division factor to the bus, and logical level 1 to the bus 23. When dividing by a mixed number, the element At the initial moment of time by the signal from the inverted output of the input signal 4 opens 15, from the output of which a single sypal arrives HaD -input of the trigger 5. The pulses from the generator 1 are fed to the C input of the trigger 5, which, together with the element I 15, works as a counting signal (Fig. 2.1: a, &, 2 ,) Through the elements of IL 18, pulses are passed to the input of the second and subsequent bits of block 21 (Fig. 2 1: e, g). When the block 21 (not including the first bit), operating in the subtraction mode, at the output of the element 14, zero level appears, logic level 1 (Fig. 2, I:) appears. The next pulse from the output of the generator 1 (Fig. 2, 1: a) the trigger 5 is switched to the zero state (Fig. 2, 1: 9), as a result of which, at the forward output of the AND element 15 (Fig. 2 1: U.) connected to the D input of the trigger. 3, the logical level 1 is set, and the inverse level is set to the logical level O, the closing element 15. The same pulse, but delayed by 0.5 periods, from the output of element 7 (Fig. 2: 6), is sent to the C input trigger 3, switches it to one state. The logical level 1 from the direct output of the trigger 3 opens the AI element; preparing the passage of the output pulse from the generator 1 through the elements 11 and 19 to the output (Fig. 2, I: K). At the same time, the signal from the trigger trigger 3 passes through the driver 17, which converts the trigger signal into a short pulse (FIG. 2, 1: J), which allows the input of the coefficient of the whole part from the bus 22 through the gate 8 to the installation inputs of the counter 20 (FIG. 2, 1: //, M), and through the element I 12 (Fig. 2, 1: / m) it switches the trigger 4 to the eddy state (Fig. 2, 1: 6), i.e. production1ggs division factor code entry. As a result of switching the trigger 4, the element AND 15 is closed, and the element 13 is opened, since the logical inputs 1, i.e. at the D-input of the trigger 6, a logic level is set (FIG. 2, 1: 5, /).) The next pulse from the output of the generator 1 passes to the output of the divider (FIG. 2, 1 o, k) and simultaneously passes through the elec- 34 ment 7, arrives at the C input of the trigger 6 (Fig. 2; I: §, c), the trigger switches with signals from the output of the element 7. After the counter is zeroed and the logic level appears, the output of the element is 9. (Fig. 2 :) Element I 14 is prepared for operation (Fig.). The next impulse from the output of element 7 switches trigger 6 to zero, the output of element 14 and, therefore, the D input of trigger 2 establishes a logic level. This trigger switches to single state from impulse 1 from generator (Fig. 2). : o1, y), preparing the output signal circuit from element 7 through elements Yu and 19 (Fig. 2: cf), ri}. At the same time, the signal from the direct output of the trigger 2, having passed through the driver 17, opens the valve 8,. the element And 12 (Fig. 2, L: l, n,, m. B) and thereby produces a new code entry. Next, the division cycle is repeated. When divided by an integer, it is necessary to send the code of the integer part of the coefficient to bus 22, and logical level O to bus 23. In this case, trigger 4 does not switch, in the first bit of block 21 one of the triggers 5 or 6 operates, depending on the state the trigger 4, in which it remains after the end of the division by the previous coefficient. With a single state of flip-flop 4 in the first discharge of block 21, flip-flop 6 operates, and the output signal is prepared by AND element 14, flip-flop 2, and the output signal passes through element 10 and 19 (Fig. 2, I). When dividing only by a fractional part equal to 0.5, logical level 0 is applied to bus 22, and logical level 1 is supplied to bus 23. In this case, block 21 does not participate in the work, since D-inputs of both triggers 5 and 6 are set Logic O levels. Counter 20 is in the zero state. At the output of element 9, a logic level is set. The state of the elements 16 and 14 and, consequently, the signals at the 1) inputs of flip-flops 3 and 2 are determined by the state of the flip-flop outputs, 4, at zero from the position of flip-flop 4, the level of the 16 the output of the element 14 and the logical o. The first pulse from the output of the element 7 switches to a single state trigger 3, which noiv prepares the passage of a signal from the gene

Rattor 1 through elements 11 and 19 on. the output and through the driver 17 and the Element Ment And 12 switches the trigger 4 to one state. The latter sets at the output of the element AND 16 the logic level O, and at the output of the element 14 and 14 - the logic level trigger 2 is prepared for operation. The pulse from generator 1 through elements 11 and 19 goes to the output, resets the trigger to the zero state via H input 3 and at the same time switches trigger 2, which prepares the passage of the signal from element 7 through elements 10 and 19 to the output and through the driver 17 and element 12 also switches the trigger 6 to the zero state. Impulse from element 7 Through elements 10 and 19 passes the output of the divider, resets trigger 2 to the R input, zero state 2, and so on. Shzl is repeated (Fig. 4.111).

The fractional factor 0.5 is divided by shifting the cycles of the pulse sequences by 0, 5 periods.

The divider is caused by failures when recording new coefficients for dividing, since the senses; .rsy-s; is set at 0.5 koachi; th,. ::, - period of eating;

3: G.,: -,: - the LCD of the NMPU, Gssa B.D for all peH-; iu ::. K is the same g is equal to the zadernske DB: I – S; g -; gkichesklementoB that is me

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Ppd, pageemop device by cpi: BKaHiiK with .podotChmMeet more speedy8 and M8YaS: th volume of equipment.

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sj;,:, the frequency of the following cpcr-s with peried kontifEggyent deed E; EH Sawyer, kav. ganertor Bm :: aulsov, jsbSKOfl kogrogO is connected to the B5sodom of the phasos of the burning element, saeivieBTH And, score. Pimples; The address of which is connected with the corresponding input signals, triggers, vhs-dm one; the second. CDS "d | 8kegs with inputs corresponding to the second and third elements AND, elements OR, about and in h and -y and with Tftivj, in order to increase the speed of the device gfE along with its simplification, it introduced the valve and the shape of the IW) nm-SupSo; The first and second inputs of which are connected to the outputs of the first and second triggers respectively, and the output to the first input of the valve, a group of inputs of which is connected to the bus for setting the code of the integer part, and the first input of the fourth element AND, the second input of which is connected to the bus for installing the fractional code parts as well the output to the input of the third trigger, the direct output of which is connected to the first inputs of the fifth and sixth elements AND, and the inverse output to the first inputs of the seventh and eighth elements And, the second inputs of which are connected to the inverse output of the fourth trigger, whose output is connected to the first input is the first OR element, the output of which is connected to the input of the pulse counter, and the second input is connected to the direct output of the fifth trigger, the inverse output of which is connected to the second inputs of the fifth and sixth elements AND, The eighth And elements are connected to the first inputs of the first and second triggers, and the inverse outputs are connected to the third inputs of the fifth and seventh elengngs Ii, respectively, whose outputs are connected to the quadruple and PET trippers, the second inputs of the first and second veins -, rpyiina vyg: odov Foroporo connect to ustsch-vochsh zP. vkodam counter IMPORTANT; treh1y Bhod the fourth trigger soedkg zn with yv; idu generator impuSOV (second-d-h first trigger and STDpbK-i Bhods.-d rpeibero element I, and the great input iii-iTOFD Tpjirrt-pa connected to the second code of the second element I, you - Phase-sludge bottom - ::: g: the secondary element and the second one; second tritter, the third input of the r-ooob connector, with the third sjieMeiJTa and eeea output, the second element of the second IL / ;, the second input of which is joint with the code of the element I and the third E: g; the house of the first trotter VZ with the 1st entrance, TJecToro to the eighth element and the connection with the output of the first element I „

The source of the Gnformat 1N, 30 received certificates at the examination of 1C / Shgorskor, certificate of the USSR 657619, k, H 03 K 23/24, 5O 12о76.

2 Copyright SESECHETALITY USSR, draft No. 3226SH.4 / 18-21, tai, H 03 K 23 / OO, 30J.2.80.

Claims (1)

F r rg “I have also been invented The variable frequency repetition factor snn snd— snss, containing a pulse generator, the output of which is connected to the input of the phase-burning element, AND elements, pulse counter * whose discharge outputs are connected to the corresponding inputs of the first element And, triggers, the outputs of the first second. On which connected to the first inputs of the second and third AND elements, respectively, OR elements, characterized in that, in order to increase the speed of the device while simplifying it, a valve is introduced into it a pulse shaper, the first and second inputs of which are connected to the outputs of the first and second triggers, respectively, and the output is connected to the first input of the valve, the group of inputs of which is connected to the setup bus of the code of the integer part, and the first input of the fourth element And, the second input of which is connected to the fractional part code setting bus, a. output - to the input of the third trigger, the direct output of which is connected to the first inputs of the fifth and sixth AND elements, and the inverse output - to the first inputs of the seventh and eighth AND elements, the second inputs of which are connected inens with the inverse output of the fourth trigger, the direct output of which is connected to the first input of the first OR element, the output of which is connected to the input of the pulse counter, and the second input - with the direct output of the fifth trigger, whose inverse output is connected to the second inputs of the fifth and sixth AND elements , while the direct outputs of the sixth and eighth AND elements are connected to the first inputs of the first and second triggers, and the inverse outputs are connected to the third inputs of the fifth and seventh AND elements, respectively, whose outputs are connected to the first inputs of even second and fifth triggers, which second inputs ?; connected to the first output of the valve, the group of outputs of which is connected to the installation inputs of the pulse counter, connect the third input of the fourth trigger about the output of the pulse generator, the second k-stroke of the first trigger and the second input of the third element And, and the third input of the trigger енητογο connected to the second input the second element AND, with the output pha.sd <'~ s »of the second element, the second input of the second trigger, the third input of which is connected to the output of the third element AND the first input of the second element OR, the second input of which is connected to the output element And and the thirdw by the input of the first trigger, while the third inputs of the sixth and eighth elements K are connected to the output of the first element I.