RU2005328C1 - Multiplier of pulse repetition frequency - Google Patents

Description

The invention relates to radio engineering and can be used to multiply the frequency in magnetic record reproducing apparatuses, and also as a measuring device that monitors the measurement of the input frequency in various radio engineering devices.

Known digital pulse repetition rate multiplier (1), containing input and output buses, a reference frequency generator, two shift registers, two blocks of AND elements, a block of OR elements, an adder, two pulse shapers, three VI elements, three pulse counters, two OR elements and a delay element with their functional relationships. The known device is characterized by insufficiently high accuracy and low noise immunity.

The closest in technical essence is a pulse repetition rate multiplier containing a pulse generator, a frequency divider, two pulse counters, three OR elements, two delay elements, a register, a pulse shaper, input and output buses, a control unit, a trigger and three AND elements with functional bonds. This multiplier reduces the operational error by reducing the number of failed situations, but does not eliminate them at all. In addition, the presence of short interference pulses in the input signal disrupts the operation of the multiplier.

The aim of the invention is to increase accuracy.

The goal is achieved in that a pulse repetition rate multiplier comprising serially connected pulse generator and synchronization unit, the second input of which is connected to the input bus, the first, second and third outputs of which and the output of the pulse generator are connected through the switch to the first, second, third and the fourth inputs of the first multiplication unit, the control unit, the first AND element and the output bus, and the delay element, the input of which is connected to the third output of the sync block, are connected in series the input and the control unit, the second input of which is connected to the third input of the synchronization unit, the series-connected second multiplication unit, the first OR element, the second input of which is connected to the output of the first multiplication unit, a pulse counter, the second input of which is connected connected to the output of the delay element, the second element And and the second

an OR element, the second input of which is combined with the second input of the pulse counter, and the output is connected to the second input of the first AND element, each of the multiplier blocks containing connected to the first input of the multiplication block, the first OR element, the first pulse counter, the output of which is combined with the second input of the first element

OR, a second OR element, a second pulse counter, the second input of which is connected to the first input of the first OR element, a frequency divider, the subtracting input of which is the fourth input of the multiplication unit, and the first delay element, the output of which is connected to the control input of the code comparison element the first group of which is connected to the bit outputs of the first pulse counter, and the output to

0 to the second input of the second element AND, and the third pulse counter, the first input of which coincides with the third input of the multiplication unit, the second input is combined with the input of the first delay element, and the bit outputs are connected to the second group of inputs of the code comparison element connected to the first input a third pulse counter connected in series to the second delay element and the third element

0 OR, the output of which is connected to the installation input of the frequency divider, and the second input to the output of the frequency divider and the second input of the third pulse counter.

In FIG. Figure 1 shows a functional 5 on an electrical circuit of a pulse repetition rate multiplier; in FIG. 2 is a diagram of a multiplication block; in FIG. 3 is a diagram of an embodiment of a synchronization unit; in FIG. 4 is a diagram of a variant of a switch; in FIG. 5 - diagram

0 control unit options; in FIG. 6 is a timing diagram illustrating the operation of a pulse repetition rate multiplier.

The pulse frequency multiplier 5 (Fig. 1) comprises a pulse generator 1, a synchronization unit 2, an input bus 3, a switch 4, a first multiplier unit 5, a control unit 6, a first I7 element, an output bus 8, a delay element 9,

0 second multiplication unit 10, first element OR11, pulse counter 12, second elements I13 and OR14 with their functional connections.

Each of the multiplication blocks 5 (10) (FIG.

5 2) contains the first element of IL15. first pulse counter 16, second element OR17, second pulse counter 18, frequency divider 19, first delay element 20, code comparison element 21, third pulse counter 22, second element 23

delays, third element OR 24 and their functional relationships.

One of the variants of the synchronization unit 2 (Fig. 3) contains a series-connected element OR25, the input of which is the third input of the synchronization unit 2, and the first trigger 26, register 27, element I28, the second input of which is combined with the first input of the synchronization unit 2 and the sync input register 27, and the third input with the second input of the synchronization unit 2 and the sync input of the first trigger 26, and the second trigger 29, the inverse and direct outputs of which are the first and second outputs of the synchronization unit 2, the third output of which is connected and 28 to the output member, wherein the second output register 27 is coupled to a second input of the first ILI25 element.

Four IZO-33 elements can be used as switch 4 (Fig. 4), the outputs of which are the fourth, third, second, and first outputs of switch 4, respectively, the first input of which is combined with the first inputs of I31 and IZZ elements, the third input with the first inputs of the elements IZO and 32, the second input with the second inputs of the elements And 32 and And 33, and the fourth input with the second inputs of the elements IZO and 31.

One of the variants of the control unit 6 (Fig. 5) contains consecutive element of the initial installation 34, the first trigger 35, the second trigger 36, the R-input of which is combined with the outputs of the element 34 of the initial installation and the second output of the control unit 6, and the element I37, the output of which is the C-input of the first trigger 35, and the second input is the input of the control unit 6, the first output of which is the second (direct) output of the second trigger 36.

The pulse repetition rate multiplier operates as follows.

The input pulses (Fig. 6a), the period of which TBx follows, come from the input bus 3 to the trigger sync input 26, translating it on the leading (positive) edge to a single state from the initial zero (Fig. 66). The first pulse from the generator 1 (Fig. 6c) transfers the single state to the first output of the register 27, and simultaneously the trigger 26 is set to the zero state. Thus, the pulse duration at the output of the register 27 (Fig. 6d) is equal to the period of the pulses from the generator 1 (T0). To eliminate short impulse noise in the input signal, an I28 element is used, at the output of which pulses are emitted (Fig. 6e) for a half-period of the signal with

generator 1 corresponding to the true pulses of the input signal and in phase with the pulses of the generator 1.

During the first (after turning on the scissors-5) period of the input signal, the multiplier is automatically prepared for operation. At this time, the output pulses of the multiplier do not reflect the reliably required dependence of the Pout. To FBx. 0 Blocking of these pulses is carried out by element I7 and block 6.

The control unit 6 operates as follows.

When the power is turned on, the element 34 produces a signal that sets the triggers 35 and 36, as well as the trigger 26 to the zero state. Element I7 is closed. After the power is turned on, the first pulse from the output of the I28 element passes through the open I37 element to the counting input of the trigger 35 and transfers it to the opposite (single) state. The next pulse from the And28 element again throws the trigger 35, on the positive edge of the output signal 5 of which the trigger 36 is reset to the ON state, opening the And7 element and closing the And37 element. Therefore, before the end of the first period of the input signal after turning on 0, the operation of the multiplier does not produce pulses at its output, the frequency of which does not reflect the required dependence of the TVT / K.

The pulse sequence from element I28 is converted by trigger 29 to 5 direct (Fig. 6e) and inverse gating sequences. Subsequently, the first block 5 of multiplication, with positive values of the direct gating sequence, measures the input 0 periods, at zero values it carries out their accelerated recounting, i.e. the frequency of the input pulse sequence is multiplied. The second multiplication block 10 operates similarly to 5 with the corresponding values of the inverse gating sequence. For the operation of blocks 5 and 10, signals are generated at the outputs of elements 32, 30, 31 and 33, respectively (Fig. 6g, h, i, k). 0 Consider the operation of the first block 5 of the multiplication. During the first input period, its duration is measured: the first pulse (Fig. 5k) is supplied to the installation inputs of the counters 18 and 16 and writes codes M - a + 1 and P-K, respectively, where M and P are the capacity of the counters; K is the multiplication coefficient, where a - -% - -

la part; PE and G24 - delay time

accordingly, the frequency divider 19 and the element OR 24: That is the period of the pulses from the generator 1..

 A packet of pulses from the generator 1 (Fig. 6g) is supplied to the summing input of the counter 16, due to feedback from the counter 16 through a OR element 15 (Fig. 6l), a series of pulses (Fig. 6m) are received from the period T0 to the summing input of the counter 18 K, thus, by the end of the first input period in the counter 1.8 will be written (Fig.

bm) the code .y BXi; . and the remainder code of this input is about.

period (О S А К) will be recorded in counter 16 (Fig. 6o).

By the second input pulse (Fig. 6p) from the I31 element, the code of the counter 18 is transferred to the divider 19, and the counter 22 is set to the state P. The delay in the element 23 is equal to t 15 + Tie + TIT Tie, in the sum of the time delays of the elements OR15 and 17 and counters 16 and 18. At the subtracting input of the frequency divider 19, a packet of pulses (Fig. 6h) comes from the IZO element. When the frequency divider .1-9 is reset, an output of a multiplied frequency pulse appears (Fig. 6p), which again writes the counter code 18 into the frequency divider 19 and subtracts one unit from the state of the counter 22 (Fig. 6p). The delay of the element 20 is slightly longer than the delay time of the counter 22. If the codes of the counters 16 and 22 are equal, then one unit will be added to the counter 18 (Fig. 6c). If, as before, counter code 16 is less than counter code 22, then the state of counter 18 will not change, because the pulse from the output of the element 20 will not pass through the element 21 and the element OR 17,

At the output of the divider 19, pulses of a multiplied frequency appear, and after adding a unit to the state of the counter 18, the time position of these pulses is corrected. Because claims

Claims (2)

1. A PULSE FREQUENCY FREQUENCY MULTIPLIER, comprising serially connected pulse generator, a synchronization unit, the second input of which is connected to the input bus, the first, second and third outputs of which and the pulse generator output are connected through the switch to the first, second, third and fourth inputs of the first block, respectively multiplications connected in series to the control unit. the first element And both the output bus and the dividing element of the divider 19 is selected by the counter code 18 and is equal to & -Ј-, and in the process IN GVH multiplication is the correction of this coefficient 5 ent, then at the output of the frequency divider 19 we have Rvykh FBX K with an accuracy of To / 2. The output signals from the frequency dividers 19 of both multiplication units 5 and 10 are combined on an OR element 11 (Fig. 6t). 0 Failure situations due to the coincidence of the pulses of the input frequency and the high frequency, as a result of which a false pulse could appear at the output of the multiplier, are fundamentally eliminated, because all signals post 5, which are located on the working part of the multiplier, are synchronous, and the durations of the installation signals are determined (normalized) by the period of pulses from the generator 1. A pulse delayed by the delay time of one multiplication block 5 (10) is transmitted to the installation input of the counter 12. The code L-K + 1 is written to the counter 12, where the L-capacity of the counter 12. Pulses from the element arrive at the summing input of the counter 12 5 OR11, the state of the counter 12 changes along the trailing edge of the pulses. The output signal of the counter 12 (Fig. 6y) prevents the last pulse of the multiplied frequency from passing through the I13 element, to the place of which a synchronous input pulse is substituted on the OR14 element (Fig. 6f). Due to this, with unequal input periods, an error is eliminated which would have happened if the last pulse had not had time to form at the output of the frequency divider 19, i.e. in the case of (TBx) i (Tex) i + i. In addition, this allows the input frequency to be multiplied with a deviation of up to ± 100 / K (%). 0 (56) 1. USSR Copyright Certificate No. 1034146, cl. H 03 B 19/10.1982, 2. USSR copyright certificate No. 1256182, cl. H 03 K5 / 156, 1984. 5 a delay moment, the input of which is connected to the third output of the synchronization unit and the input of the control unit, the second input of which is a CIRCU connected to the third input of the synchronization unit, characterized in that. in order to improve accuracy, it introduced the second multiplication unit connected in series to the corresponding outputs of the switch, the first OR element, the second input of which is connected to the output of the first multiplication unit, a pulse counter, the second input of which is connected to the output of the element .... Holds, the second AND element and the second OR element, the second input of which is combined with the second input of the pulse counter, and the output is connected to the second input of the first element I. 2. The multiplier according to claim 1, characterized in that each of the multiplication units contains I connected to the first input of the multiplication unit in series with the first OR element, the first pulse counter, the output of which is combined with the second input of the first OR element, the second OR element, a second pulse counter, the second input of which is connected to the first input of the first OR element, a frequency divider, the subtracting input of which is the input of the multiplication unit, and the first delay element, the output of which is connected to the control input 0 5 0 there is a code comparison element, the first group of inputs of which is connected to the bit outputs of the first pulse counter, and the output to the second input of the second OR element. and a third pulse counter, the first input of which coincides with the third input of the multiplication unit, the second input is combined with the input of the first delay element, and the bit outputs are connected to the second group of inputs of the code comparison element, connected to the first input of the third pulse counter, connected in series to the second delay element and the third OR element, the output of which is connected to the installation input of the frequency divider, and the second input to the output of the frequency divider and the second input of the third pulse counter. FIG. 2      #Wf 1 fig.Z Fog. 4  eleven FIG. 5 P AND L V-ji  V 4 JUU1L "/ l) c; i I im f /. All I II I U -vXlXlXUO UV L J i j t U - jj VVV TXU V .. 5A D V /. Y /.  -n. n p i- in l and j i. g Fi. € Jljuljulljl Jl JLJJULJLJLJ n n n II JL I fl fl I YAI g Jl w l 1 1 JLJ LJLJULJL g i / iJi i -d -vXlXlXUO UV L Jl JLJJULJLJLJ