SG92654A1 - Method and system for testing integrated circuit devices at the wafer level - Google Patents

Method and system for testing integrated circuit devices at the wafer level

Info

Publication number
SG92654A1
SG92654A1 SG9904662A SG1999004662A SG92654A1 SG 92654 A1 SG92654 A1 SG 92654A1 SG 9904662 A SG9904662 A SG 9904662A SG 1999004662 A SG1999004662 A SG 1999004662A SG 92654 A1 SG92654 A1 SG 92654A1
Authority
SG
Singapore
Prior art keywords
integrated circuit
wafer level
circuit devices
testing integrated
testing
Prior art date
Application number
SG9904662A
Other languages
English (en)
Inventor
Dasgupta Sumit
Srikrishnan Kris
Gene Walther Ronald
Original Assignee
Ibm
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibm filed Critical Ibm
Publication of SG92654A1 publication Critical patent/SG92654A1/en

Links

SG9904662A 1998-09-29 1999-09-17 Method and system for testing integrated circuit devices at the wafer level SG92654A1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US16282698A 1998-09-29 1998-09-29

Publications (1)

Publication Number Publication Date
SG92654A1 true SG92654A1 (en) 2002-11-19

Family

ID=22587288

Family Applications (1)

Application Number Title Priority Date Filing Date
SG9904662A SG92654A1 (en) 1998-09-29 1999-09-17 Method and system for testing integrated circuit devices at the wafer level

Country Status (3)

Country Link
KR (1) KR100313185B1 (ko)
CN (1) CN1249534A (ko)
SG (1) SG92654A1 (ko)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4234244B2 (ja) * 1998-12-28 2009-03-04 富士通マイクロエレクトロニクス株式会社 ウエハーレベルパッケージ及びウエハーレベルパッケージを用いた半導体装置の製造方法
KR100389905B1 (ko) * 2001-03-22 2003-07-04 삼성전자주식회사 기판단위의 품질측정을 위한 용량형 소자 어레이 및 그제조방법
US6882546B2 (en) 2001-10-03 2005-04-19 Formfactor, Inc. Multiple die interconnect system
KR101918608B1 (ko) 2012-02-28 2018-11-14 삼성전자 주식회사 반도체 패키지
CN103197227A (zh) * 2013-03-25 2013-07-10 西安华芯半导体有限公司 一种用于设计分析目的的晶圆测试方法
CN116338442B (zh) * 2023-05-30 2023-08-04 深圳市微特精密科技股份有限公司 一种dut的边界扫描测试系统及自检测方法

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4288911A (en) * 1979-12-21 1981-09-15 Harris Corporation Method for qualifying biased integrated circuits on a wafer level
WO1982002603A1 (en) * 1981-01-16 1982-08-05 Robert Royce Johnson Wafer and method of testing networks thereon
EP0405586B1 (en) * 1989-06-30 1997-03-26 Kabushiki Kaisha Toshiba Semiconductor device and method of burning in the same
US5654588A (en) * 1993-07-23 1997-08-05 Motorola Inc. Apparatus for performing wafer-level testing of integrated circuits where the wafer uses a segmented conductive top-layer bus structure
US5898186A (en) * 1996-09-13 1999-04-27 Micron Technology, Inc. Reduced terminal testing system

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4288911A (en) * 1979-12-21 1981-09-15 Harris Corporation Method for qualifying biased integrated circuits on a wafer level
WO1982002603A1 (en) * 1981-01-16 1982-08-05 Robert Royce Johnson Wafer and method of testing networks thereon
EP0405586B1 (en) * 1989-06-30 1997-03-26 Kabushiki Kaisha Toshiba Semiconductor device and method of burning in the same
US5654588A (en) * 1993-07-23 1997-08-05 Motorola Inc. Apparatus for performing wafer-level testing of integrated circuits where the wafer uses a segmented conductive top-layer bus structure
US5898186A (en) * 1996-09-13 1999-04-27 Micron Technology, Inc. Reduced terminal testing system

Also Published As

Publication number Publication date
KR100313185B1 (ko) 2001-11-07
KR20000022722A (ko) 2000-04-25
CN1249534A (zh) 2000-04-05

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