SG92654A1 - Method and system for testing integrated circuit devices at the wafer level - Google Patents
Method and system for testing integrated circuit devices at the wafer levelInfo
- Publication number
- SG92654A1 SG92654A1 SG9904662A SG1999004662A SG92654A1 SG 92654 A1 SG92654 A1 SG 92654A1 SG 9904662 A SG9904662 A SG 9904662A SG 1999004662 A SG1999004662 A SG 1999004662A SG 92654 A1 SG92654 A1 SG 92654A1
- Authority
- SG
- Singapore
- Prior art keywords
- integrated circuit
- wafer level
- circuit devices
- testing integrated
- testing
- Prior art date
Links
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US16282698A | 1998-09-29 | 1998-09-29 |
Publications (1)
Publication Number | Publication Date |
---|---|
SG92654A1 true SG92654A1 (en) | 2002-11-19 |
Family
ID=22587288
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
SG9904662A SG92654A1 (en) | 1998-09-29 | 1999-09-17 | Method and system for testing integrated circuit devices at the wafer level |
Country Status (3)
Country | Link |
---|---|
KR (1) | KR100313185B1 (en) |
CN (1) | CN1249534A (en) |
SG (1) | SG92654A1 (en) |
Families Citing this family (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP4234244B2 (en) | 1998-12-28 | 2009-03-04 | 富士通マイクロエレクトロニクス株式会社 | Wafer level package and semiconductor device manufacturing method using wafer level package |
KR100389905B1 (en) * | 2001-03-22 | 2003-07-04 | 삼성전자주식회사 | Capacitive device array and fabricating method thereof |
US6882546B2 (en) * | 2001-10-03 | 2005-04-19 | Formfactor, Inc. | Multiple die interconnect system |
KR101918608B1 (en) | 2012-02-28 | 2018-11-14 | 삼성전자 주식회사 | Semiconductor package |
CN103197227A (en) * | 2013-03-25 | 2013-07-10 | 西安华芯半导体有限公司 | Wafer testing method used for design analysis purpose |
CN116338442B (en) * | 2023-05-30 | 2023-08-04 | 深圳市微特精密科技股份有限公司 | Boundary scanning test system and self-detection method of DUT |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4288911A (en) * | 1979-12-21 | 1981-09-15 | Harris Corporation | Method for qualifying biased integrated circuits on a wafer level |
WO1982002603A1 (en) * | 1981-01-16 | 1982-08-05 | Robert Royce Johnson | Wafer and method of testing networks thereon |
EP0405586B1 (en) * | 1989-06-30 | 1997-03-26 | Kabushiki Kaisha Toshiba | Semiconductor device and method of burning in the same |
US5654588A (en) * | 1993-07-23 | 1997-08-05 | Motorola Inc. | Apparatus for performing wafer-level testing of integrated circuits where the wafer uses a segmented conductive top-layer bus structure |
US5898186A (en) * | 1996-09-13 | 1999-04-27 | Micron Technology, Inc. | Reduced terminal testing system |
-
1999
- 1999-08-14 KR KR1019990033497A patent/KR100313185B1/en not_active IP Right Cessation
- 1999-09-16 CN CN 99118883 patent/CN1249534A/en active Pending
- 1999-09-17 SG SG9904662A patent/SG92654A1/en unknown
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4288911A (en) * | 1979-12-21 | 1981-09-15 | Harris Corporation | Method for qualifying biased integrated circuits on a wafer level |
WO1982002603A1 (en) * | 1981-01-16 | 1982-08-05 | Robert Royce Johnson | Wafer and method of testing networks thereon |
EP0405586B1 (en) * | 1989-06-30 | 1997-03-26 | Kabushiki Kaisha Toshiba | Semiconductor device and method of burning in the same |
US5654588A (en) * | 1993-07-23 | 1997-08-05 | Motorola Inc. | Apparatus for performing wafer-level testing of integrated circuits where the wafer uses a segmented conductive top-layer bus structure |
US5898186A (en) * | 1996-09-13 | 1999-04-27 | Micron Technology, Inc. | Reduced terminal testing system |
Also Published As
Publication number | Publication date |
---|---|
KR20000022722A (en) | 2000-04-25 |
KR100313185B1 (en) | 2001-11-07 |
CN1249534A (en) | 2000-04-05 |
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