SG88762A1 - Miniaturized semiconductor package arrangement - Google Patents

Miniaturized semiconductor package arrangement

Info

Publication number
SG88762A1
SG88762A1 SG9905373A SG1999005373A SG88762A1 SG 88762 A1 SG88762 A1 SG 88762A1 SG 9905373 A SG9905373 A SG 9905373A SG 1999005373 A SG1999005373 A SG 1999005373A SG 88762 A1 SG88762 A1 SG 88762A1
Authority
SG
Singapore
Prior art keywords
semiconductor package
package arrangement
miniaturized semiconductor
miniaturized
arrangement
Prior art date
Application number
SG9905373A
Other languages
English (en)
Inventor
Tze-You Chen William
Original Assignee
Ibm
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibm filed Critical Ibm
Publication of SG88762A1 publication Critical patent/SG88762A1/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157—Partial encapsulation or coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/4824—Connecting between the body and an opposite side of the item with respect to the body
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    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73215—Layer and wire connectors
    • H—ELECTRICITY
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    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/8538—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/85399—Material
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
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    • H01L2924/01016—Sulfur [S]
    • H—ELECTRICITY
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    • H01L2924/01033—Arsenic [As]
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/156—Material
    • H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H01L2924/15787—Ceramics, e.g. crystalline carbides, nitrides or oxides
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Wire Bonding (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
SG9905373A 1998-11-02 1999-10-29 Miniaturized semiconductor package arrangement SG88762A1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US09/184,839 US6429530B1 (en) 1998-11-02 1998-11-02 Miniaturized chip scale ball grid array semiconductor package

Publications (1)

Publication Number Publication Date
SG88762A1 true SG88762A1 (en) 2002-05-21

Family

ID=22678577

Family Applications (1)

Application Number Title Priority Date Filing Date
SG9905373A SG88762A1 (en) 1998-11-02 1999-10-29 Miniaturized semiconductor package arrangement

Country Status (6)

Country Link
US (1) US6429530B1 (ko)
KR (1) KR100353170B1 (ko)
CN (1) CN1222993C (ko)
HK (1) HK1027903A1 (ko)
MY (1) MY123455A (ko)
SG (1) SG88762A1 (ko)

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US7105923B2 (en) * 2001-12-28 2006-09-12 Texas Instruments Incorporated Device and method for including passive components in a chip scale package
US6521846B1 (en) 2002-01-07 2003-02-18 Sun Microsystems, Inc. Method for assigning power and ground pins in array packages to enhance next level routing
US7109574B2 (en) * 2002-07-26 2006-09-19 Stmicroelectronics, Inc. Integrated circuit package with exposed die surfaces and auxiliary attachment
US6667191B1 (en) * 2002-08-05 2003-12-23 Asat Ltd. Chip scale integrated circuit package
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US7262508B2 (en) * 2003-10-03 2007-08-28 Avago Technologies General Ip (Singapore) Pte. Ltd. Integrated circuit incorporating flip chip and wire bonding
US20050087883A1 (en) * 2003-10-22 2005-04-28 Advanpack Solutions Pte. Ltd. Flip chip package using no-flow underfill and method of fabrication
DE102004007690B3 (de) * 2004-02-16 2005-10-13 Infineon Technologies Ag Integrierte Schaltungsanordnung
TWI324380B (en) * 2006-12-06 2010-05-01 Princo Corp Hybrid structure of multi-layer substrates and manufacture method thereof
US8169078B2 (en) * 2006-12-28 2012-05-01 Renesas Electronics Corporation Electrode structure, semiconductor element, and methods of manufacturing the same
DE102007043526B4 (de) * 2007-09-12 2020-10-08 Robert Bosch Gmbh Verfahren zum Herstellen einer Vielzahl von Chips und entsprechend hergestellter Chip
WO2009128047A1 (en) * 2008-04-18 2009-10-22 Nxp B.V. High density inductor, having a high quality factor
US8642381B2 (en) 2010-07-16 2014-02-04 Stats Chippac, Ltd. Semiconductor device and method of forming protective layer over exposed surfaces of semiconductor die
US8895440B2 (en) 2010-08-06 2014-11-25 Stats Chippac, Ltd. Semiconductor die and method of forming Fo-WLCSP vertical interconnect using TSV and TMV
TWI434249B (zh) 2010-11-11 2014-04-11 Au Optronics Corp 顯示裝置及其製作方法
CN102184905A (zh) * 2011-04-26 2011-09-14 哈尔滨工业大学 单金属间化合物微互连焊点结构
US8993378B2 (en) * 2011-09-06 2015-03-31 Taiwan Semiconductor Manufacturing Co., Ltd. Flip-chip BGA assembly process
CN103047556A (zh) * 2012-09-14 2013-04-17 孙百贵 基于cob器件的led灯具的制造方法
US10529697B2 (en) * 2016-09-16 2020-01-07 Taiwan Semiconductor Manufacturing Company, Ltd. Package structure and method of forming the same
KR102404058B1 (ko) 2017-12-28 2022-05-31 삼성전자주식회사 반도체 패키지
JP7289719B2 (ja) * 2019-05-17 2023-06-12 新光電気工業株式会社 半導体装置、半導体装置アレイ

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US6005290A (en) * 1992-03-06 1999-12-21 Micron Technology, Inc. Multi chip module having self limiting contact members
EP0771029A2 (en) * 1995-10-24 1997-05-02 Oki Electric Industry Co., Ltd. Semiconductor device having an improved structure for preventing cracks, and method of manufacturing the same
US6177725B1 (en) * 1995-10-24 2001-01-23 Oki Electric Industry Co., Ltd. Semiconductor device having an improved structure for preventing cracks, improved small-sized semiconductor and method of manufacturing the same
US5889332A (en) * 1997-02-21 1999-03-30 Hewlett-Packard Company Area matched package
US6091140A (en) * 1998-10-23 2000-07-18 Texas Instruments Incorporated Thin chip-size integrated circuit package
JP2001044226A (ja) * 1999-07-27 2001-02-16 Mitsubishi Electric Corp 半導体装置の製造方法および半導体装置

Also Published As

Publication number Publication date
CN1222993C (zh) 2005-10-12
KR100353170B1 (ko) 2002-09-18
MY123455A (en) 2006-05-31
US6429530B1 (en) 2002-08-06
HK1027903A1 (en) 2001-01-23
KR20000035020A (ko) 2000-06-26
CN1254185A (zh) 2000-05-24

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