SG43847A1 - Cpu-bus controller - Google Patents

Cpu-bus controller

Info

Publication number
SG43847A1
SG43847A1 SG1996002138A SG1996002138A SG43847A1 SG 43847 A1 SG43847 A1 SG 43847A1 SG 1996002138 A SG1996002138 A SG 1996002138A SG 1996002138 A SG1996002138 A SG 1996002138A SG 43847 A1 SG43847 A1 SG 43847A1
Authority
SG
Singapore
Prior art keywords
cpu
bus controller
bus
controller
Prior art date
Application number
SG1996002138A
Other languages
English (en)
Inventor
Ronald J Larson
Original Assignee
Ast Research Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ast Research Inc filed Critical Ast Research Inc
Publication of SG43847A1 publication Critical patent/SG43847A1/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4221—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus
    • G06F13/423—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus with synchronous protocol

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Bus Control (AREA)
  • Information Transfer Systems (AREA)
SG1996002138A 1989-10-11 1990-10-11 Cpu-bus controller SG43847A1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/419,096 US5220651A (en) 1989-10-11 1989-10-11 Cpu-bus controller for accomplishing transfer operations between a controller and devices coupled to an input/output bus

Publications (1)

Publication Number Publication Date
SG43847A1 true SG43847A1 (en) 1997-11-14

Family

ID=23660769

Family Applications (1)

Application Number Title Priority Date Filing Date
SG1996002138A SG43847A1 (en) 1989-10-11 1990-10-11 Cpu-bus controller

Country Status (7)

Country Link
US (1) US5220651A (de)
EP (1) EP0423036B1 (de)
JP (1) JP3302357B2 (de)
KR (1) KR0156922B1 (de)
CA (1) CA2026068A1 (de)
DE (1) DE69032783T2 (de)
SG (1) SG43847A1 (de)

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JP2776390B2 (ja) * 1989-11-30 1998-07-16 富士通株式会社 送信系及び受信系バスインタフェース
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US5353417A (en) * 1991-05-28 1994-10-04 International Business Machines Corp. Personal computer with bus interface controller coupled directly with local processor and input/output data buses and for anticipating memory control changes on arbitration for bus access
US5418930A (en) * 1991-09-05 1995-05-23 International Business Machines Corporation Circuit for interfacing asynchronous to synchronous communications
US5511229A (en) * 1991-09-13 1996-04-23 Matsushita Electric Industrial Co., Ltd. Data processing system having a switching network connecting multiple peripheral devices using data paths capable of different data bus widths
US5341508A (en) * 1991-10-04 1994-08-23 Bull Hn Information Systems Inc. Processing unit having multiple synchronous bus for sharing access and regulating system bus access to synchronous bus
US5341495A (en) * 1991-10-04 1994-08-23 Bull Hn Information Systems, Inc. Bus controller having state machine for translating commands and controlling accesses from system bus to synchronous bus having different bus protocols
JPH0619466A (ja) * 1992-07-01 1994-01-28 Kawai Musical Instr Mfg Co Ltd 音楽情報処理システム
US5469547A (en) * 1992-07-17 1995-11-21 Digital Equipment Corporation Asynchronous bus interface for generating individual handshake signal for each data transfer based on associated propagation delay within a transaction
US5745791A (en) * 1992-09-16 1998-04-28 Intel Corporation System for interfacing first and second components having different data path width by generating first and second component address to read data into buffer
US5299315A (en) * 1992-09-17 1994-03-29 International Business Machines Corp. Personal computer with programmable threshold FIFO registers for data transfer
TW276312B (de) * 1992-10-20 1996-05-21 Cirrlis Logic Inc
JP3369227B2 (ja) * 1992-11-09 2003-01-20 株式会社東芝 プロセッサ
US5499384A (en) * 1992-12-31 1996-03-12 Seiko Epson Corporation Input output control unit having dedicated paths for controlling the input and output of data between host processor and external device
US5649162A (en) * 1993-05-24 1997-07-15 Micron Electronics, Inc. Local bus interface
US5513372A (en) * 1993-08-23 1996-04-30 Intel Corporation Peripheral interface having hold control logic for generating stall signals to arbitrate two read and one write operations between processor and peripheral
US5426740A (en) * 1994-01-14 1995-06-20 Ast Research, Inc. Signaling protocol for concurrent bus access in a multiprocessor system
US5678064A (en) * 1994-12-01 1997-10-14 International Business Machines Corporation Local bus-ISA bridge for supporting PIO and third party DMA data transfers to IDE drives
US5682508A (en) * 1995-03-23 1997-10-28 Onset Computer Corporation UART protocol that provides predictable delay for communication between computers of disparate ability
US5867672A (en) * 1996-05-21 1999-02-02 Integrated Device Technology, Inc. Triple-bus FIFO buffers that can be chained together to increase buffer depth
JPH1078934A (ja) * 1996-07-01 1998-03-24 Sun Microsyst Inc パケット切替えコンピュータ・システムのマルチサイズ・バス結合システム
US6230216B1 (en) * 1999-01-28 2001-05-08 Vlsi Technology, Inc. Method for eliminating dual address cycles in a peripheral component interconnect environment
JP3886870B2 (ja) 2002-09-06 2007-02-28 株式会社ルネサステクノロジ データ処理装置
JP4542308B2 (ja) * 2002-12-16 2010-09-15 株式会社ソニー・コンピュータエンタテインメント 信号処理用デバイス及び情報処理機器
EP1619588B1 (de) * 2004-07-21 2007-05-09 STMicroelectronics Limited Speicherzugriff
US20070073932A1 (en) * 2005-09-13 2007-03-29 Alcatel Method and apparatus for a configurable data path interface
US8667254B1 (en) * 2008-05-15 2014-03-04 Xilinx, Inc. Method and apparatus for processing data in an embedded system
CN103198043B (zh) * 2013-01-24 2016-05-11 杭州中科微电子有限公司 一种改进的AHB to APB总线桥及其控制方法
US9543044B2 (en) * 2013-11-07 2017-01-10 Stmicroelectronics International N.V. System and method for improving memory performance and identifying weak bits
KR200483746Y1 (ko) 2015-07-24 2017-07-03 퍼니피쉬(주) 램프

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US4562533A (en) * 1981-12-03 1985-12-31 Ncr Corporation Data communications system to system adapter
US4476527A (en) * 1981-12-10 1984-10-09 Data General Corporation Synchronous data bus with automatically variable data rate
US4580213A (en) * 1982-07-07 1986-04-01 Motorola, Inc. Microprocessor capable of automatically performing multiple bus cycles
US4602327A (en) * 1983-07-28 1986-07-22 Motorola, Inc. Bus master capable of relinquishing bus on request and retrying bus cycle
KR900007564B1 (ko) * 1984-06-26 1990-10-15 모토로라 인코포레이티드 동적 버스를 갖는 데이터 처리기
US4835681A (en) * 1984-06-27 1989-05-30 Compaq Computer Corporation Personal computer having normal and high speed execution modes
US4727491A (en) * 1984-06-27 1988-02-23 Compaq Computer Corporation Personal computer having normal and high speed execution modes
BG39765A1 (en) * 1985-02-14 1986-08-15 Turlakov Device for connecting 8- degree and 16- degree modules to 16- degree microprocessor system
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US4987529A (en) * 1988-08-11 1991-01-22 Ast Research, Inc. Shared memory bus system for arbitrating access control among contending memory refresh circuits, peripheral controllers, and bus masters

Also Published As

Publication number Publication date
JP3302357B2 (ja) 2002-07-15
DE69032783D1 (de) 1999-01-07
KR0156922B1 (ko) 1998-11-16
JPH03208153A (ja) 1991-09-11
CA2026068A1 (en) 1991-04-12
US5220651A (en) 1993-06-15
EP0423036B1 (de) 1998-11-25
KR910008589A (ko) 1991-05-31
DE69032783T2 (de) 1999-07-01
EP0423036A3 (en) 1991-09-25
EP0423036A2 (de) 1991-04-17

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