SG191463A1 - Semiconductor packaging method and structure thereof - Google Patents

Semiconductor packaging method and structure thereof Download PDF

Info

Publication number
SG191463A1
SG191463A1 SG2012069548A SG2012069548A SG191463A1 SG 191463 A1 SG191463 A1 SG 191463A1 SG 2012069548 A SG2012069548 A SG 2012069548A SG 2012069548 A SG2012069548 A SG 2012069548A SG 191463 A1 SG191463 A1 SG 191463A1
Authority
SG
Singapore
Prior art keywords
copper
semiconductor packaging
dissociation
accordance
linking
Prior art date
Application number
SG2012069548A
Other languages
English (en)
Inventor
Shih Cheng-Hung
Lin Shu-Chen
Lin Cheng-Fan
Hsieh Yung-Wei
Liu Ming-Yi
Original Assignee
Chipbond Technology Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Chipbond Technology Corp filed Critical Chipbond Technology Corp
Publication of SG191463A1 publication Critical patent/SG191463A1/en

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73203Bump and layer connectors
    • H01L2224/73204Bump and layer connectors the bump connector being embedded into the layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92Specific sequence of method steps
    • H01L2224/921Connecting a surface with connectors of different types
    • H01L2224/9212Sequential connecting processes
    • H01L2224/92122Sequential connecting processes the first connecting process involving a bump connector
    • H01L2224/92125Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)
SG2012069548A 2012-01-03 2012-09-19 Semiconductor packaging method and structure thereof SG191463A1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW101100127A TWI463585B (zh) 2012-01-03 2012-01-03 半導體封裝方法及其結構

Publications (1)

Publication Number Publication Date
SG191463A1 true SG191463A1 (en) 2013-07-31

Family

ID=48992266

Family Applications (1)

Application Number Title Priority Date Filing Date
SG2012069548A SG191463A1 (en) 2012-01-03 2012-09-19 Semiconductor packaging method and structure thereof

Country Status (4)

Country Link
JP (1) JP2013140936A (ko)
KR (1) KR101419329B1 (ko)
SG (1) SG191463A1 (ko)
TW (1) TWI463585B (ko)

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3633422B2 (ja) * 2000-02-22 2005-03-30 ソニーケミカル株式会社 接続材料
TWI248221B (en) * 2005-05-05 2006-01-21 Po-Chien Li Bump structure of LED flip chip
JP4993880B2 (ja) * 2005-07-06 2012-08-08 旭化成イーマテリアルズ株式会社 異方導電性接着シート及び微細接続構造体
TW200812027A (en) * 2006-08-22 2008-03-01 Int Semiconductor Tech Ltd Flip-chip attach structure and method
KR101116167B1 (ko) * 2007-10-29 2012-03-06 한양대학교 산학협력단 금속 복합 범프 형성 및 이를 이용한 접합 방법
JPWO2009122867A1 (ja) * 2008-03-31 2011-07-28 日本電気株式会社 半導体装置、複合回路装置及びそれらの製造方法
WO2009139153A1 (ja) * 2008-05-16 2009-11-19 住友ベークライト株式会社 半導体部品の製造方法および半導体部品
WO2010013728A1 (ja) * 2008-07-31 2010-02-04 日本電気株式会社 半導体装置及びその製造方法
JP5296116B2 (ja) * 2011-02-16 2013-09-25 シャープ株式会社 半導体装置
JP2012212864A (ja) * 2011-03-18 2012-11-01 Sekisui Chem Co Ltd 接続構造体の製造方法及び接続構造体
TWM428492U (en) * 2012-01-03 2012-05-01 Chipbond Technology Corp Semiconductor packaging structure

Also Published As

Publication number Publication date
TW201330125A (zh) 2013-07-16
TWI463585B (zh) 2014-12-01
KR101419329B1 (ko) 2014-07-14
KR20130079980A (ko) 2013-07-11
JP2013140936A (ja) 2013-07-18

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